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Searched refs:sdma_offsets (Results 1 – 4 of 4) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v3_0.c74 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
579 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in sdma_v3_0_ctx_switch_enable()
586 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i], in sdma_v3_0_ctx_switch_enable()
588 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i], in sdma_v3_0_ctx_switch_enable()
598 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); in sdma_v3_0_ctx_switch_enable()
661 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], in sdma_v3_0_gfx_resume()
679 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume()
681 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume()
682 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume()
716 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in sdma_v3_0_gfx_resume()
[all …]
H A Dcik_sdma.c47 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
196 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], in cik_sdma_ring_set_wptr()
318 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0); in cik_sdma_gfx_stop()
372 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); in cik_ctx_switch_enable()
387 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl); in cik_ctx_switch_enable()
448 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], in cik_sdma_gfx_resume()
464 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); in cik_sdma_gfx_resume()
465 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in cik_sdma_gfx_resume()
466 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); in cik_sdma_gfx_resume()
484 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], in cik_sdma_gfx_resume()
[all …]
H A Dsdma_v2_4.c60 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = { variable
384 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); in sdma_v2_4_enable()
389 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl); in sdma_v2_4_enable()
416 WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
421 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i], in sdma_v2_4_gfx_resume()
438 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
439 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
440 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
441 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); in sdma_v2_4_gfx_resume()
444 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i], in sdma_v2_4_gfx_resume()
[all …]
H A Dsi_dma.c30 const u32 sdma_offsets[SDMA_MAX_INSTANCE] = variable
120 rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); in si_dma_stop()
122 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_stop()
137 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0); in si_dma_start()
145 WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); in si_dma_start()
148 WREG32(DMA_RB_RPTR + sdma_offsets[i], 0); in si_dma_start()
149 WREG32(DMA_RB_WPTR + sdma_offsets[i], 0); in si_dma_start()
165 WREG32(DMA_IB_CNTL + sdma_offsets[i], ib_cntl); in si_dma_start()
167 dma_cntl = RREG32(DMA_CNTL + sdma_offsets[i]); in si_dma_start()
169 WREG32(DMA_CNTL + sdma_offsets[i], dma_cntl); in si_dma_start()
[all …]