47 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =  variable
182 	return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) & 0x3fffc) >> 2;  in cik_sdma_ring_get_wptr()
196 	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me],  in cik_sdma_ring_set_wptr()
315 		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);  in cik_sdma_gfx_stop()
317 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);  in cik_sdma_gfx_stop()
318 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_stop()
372 		f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);  in cik_ctx_switch_enable()
377 				WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],  in cik_ctx_switch_enable()
379 				WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],  in cik_ctx_switch_enable()
387 		WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);  in cik_ctx_switch_enable()
410 		me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);  in cik_sdma_enable()
415 		WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);  in cik_sdma_enable()
441 			WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
442 			WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
448 		WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],  in cik_sdma_gfx_resume()
451 		WREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
452 		WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
461 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);  in cik_sdma_gfx_resume()
464 		WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
465 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
466 		WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
467 		WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);  in cik_sdma_gfx_resume()
470 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],  in cik_sdma_gfx_resume()
472 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],  in cik_sdma_gfx_resume()
477 		WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);  in cik_sdma_gfx_resume()
478 		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);  in cik_sdma_gfx_resume()
481 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);  in cik_sdma_gfx_resume()
484 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i],  in cik_sdma_gfx_resume()
492 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);  in cik_sdma_gfx_resume()
551 		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);  in cik_sdma_load_microcode()
553 			WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));  in cik_sdma_load_microcode()
554 		WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);  in cik_sdma_load_microcode()