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Searched refs:sdma_cntl (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dsi_dma.c580 u32 sdma_cntl; in si_dma_set_trap_irq_state() local
586 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
587 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
588 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
591 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
592 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
593 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
603 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
604 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
608 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
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H A Dsdma_v2_4.c989 u32 sdma_cntl; in sdma_v2_4_set_trap_irq_state() local
995 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
996 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
997 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1000 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v2_4_set_trap_irq_state()
1001 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
1002 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1012 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v2_4_set_trap_irq_state()
1013 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v2_4_set_trap_irq_state()
1017 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v2_4_set_trap_irq_state()
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H A Dsdma_v3_0.c1327 u32 sdma_cntl; in sdma_v3_0_set_trap_irq_state() local
1333 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1334 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1335 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1338 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in sdma_v3_0_set_trap_irq_state()
1339 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
1340 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1350 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0); in sdma_v3_0_set_trap_irq_state()
1351 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in sdma_v3_0_set_trap_irq_state()
1355 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1); in sdma_v3_0_set_trap_irq_state()
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H A Dcik_sdma.c1100 u32 sdma_cntl; in cik_sdma_set_trap_irq_state() local
1106 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1107 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
1108 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1111 sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET); in cik_sdma_set_trap_irq_state()
1112 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
1113 WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1123 sdma_cntl &= ~SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
1124 WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl); in cik_sdma_set_trap_irq_state()
1128 sdma_cntl |= SDMA0_CNTL__TRAP_ENABLE_MASK; in cik_sdma_set_trap_irq_state()
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H A Dsdma_v4_4_2.c1757 u32 sdma_cntl; in sdma_v4_4_2_set_trap_irq_state() local
1759 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); in sdma_v4_4_2_set_trap_irq_state()
1760 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, TRAP_ENABLE, in sdma_v4_4_2_set_trap_irq_state()
1762 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); in sdma_v4_4_2_set_trap_irq_state()
1856 u32 sdma_cntl; in sdma_v4_4_2_set_ecc_irq_state() local
1858 sdma_cntl = RREG32_SDMA(type, regSDMA_CNTL); in sdma_v4_4_2_set_ecc_irq_state()
1859 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA_CNTL, DRAM_ECC_INT_ENABLE, in sdma_v4_4_2_set_ecc_irq_state()
1861 WREG32_SDMA(type, regSDMA_CNTL, sdma_cntl); in sdma_v4_4_2_set_ecc_irq_state()
H A Dsdma_v7_0.c1519 u32 sdma_cntl; in sdma_v7_0_set_trap_irq_state() local
1523 sdma_cntl = RREG32(reg_offset); in sdma_v7_0_set_trap_irq_state()
1524 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v7_0_set_trap_irq_state()
1526 WREG32(reg_offset, sdma_cntl); in sdma_v7_0_set_trap_irq_state()
H A Dsdma_v6_0.c1539 u32 sdma_cntl; in sdma_v6_0_set_trap_irq_state() local
1544 sdma_cntl = RREG32(reg_offset); in sdma_v6_0_set_trap_irq_state()
1545 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v6_0_set_trap_irq_state()
1547 WREG32(reg_offset, sdma_cntl); in sdma_v6_0_set_trap_irq_state()
H A Dsdma_v5_2.c1612 u32 sdma_cntl; in sdma_v5_2_set_trap_irq_state() local
1616 sdma_cntl = RREG32(reg_offset); in sdma_v5_2_set_trap_irq_state()
1617 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_2_set_trap_irq_state()
1619 WREG32(reg_offset, sdma_cntl); in sdma_v5_2_set_trap_irq_state()
H A Dsdma_v5_0.c1711 u32 sdma_cntl; in sdma_v5_0_set_trap_irq_state() local
1718 sdma_cntl = RREG32(reg_offset); in sdma_v5_0_set_trap_irq_state()
1719 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v5_0_set_trap_irq_state()
1721 WREG32(reg_offset, sdma_cntl); in sdma_v5_0_set_trap_irq_state()
H A Dsdma_v4_0.c2064 u32 sdma_cntl; in sdma_v4_0_set_trap_irq_state() local
2066 sdma_cntl = RREG32_SDMA(type, mmSDMA0_CNTL); in sdma_v4_0_set_trap_irq_state()
2067 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, in sdma_v4_0_set_trap_irq_state()
2069 WREG32_SDMA(type, mmSDMA0_CNTL, sdma_cntl); in sdma_v4_0_set_trap_irq_state()