Lines Matching refs:sdma_cntl
580 u32 sdma_cntl; in si_dma_set_trap_irq_state() local
586 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
587 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
588 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
591 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
592 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
593 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
602 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
603 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
604 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
607 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
608 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
609 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()