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Searched refs:reg_entry (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/arch/powerpc/platforms/powernv/
H A Dopal-fadump.h129 struct hdat_fadump_reg_entry *reg_entry; in opal_fadump_read_regs() local
136 reg_entry = (struct hdat_fadump_reg_entry *)bufp; in opal_fadump_read_regs()
137 val = (cpu_endian ? be64_to_cpu(reg_entry->reg_val) : in opal_fadump_read_regs()
138 (u64 __force)(reg_entry->reg_val)); in opal_fadump_read_regs()
140 be32_to_cpu(reg_entry->reg_type), in opal_fadump_read_regs()
141 be32_to_cpu(reg_entry->reg_num), in opal_fadump_read_regs()
/linux-6.15/arch/powerpc/platforms/pseries/
H A Drtas-fadump.h111 #define RTAS_FADUMP_SKIP_TO_NEXT_CPU(reg_entry) \ argument
113 while (be64_to_cpu(reg_entry->reg_id) != \
115 reg_entry++; \
116 reg_entry++; \
H A Drtas-fadump.c340 be64_to_cpu(reg_entry->reg_value)); in rtas_fadump_read_regs()
341 reg_entry++; in rtas_fadump_read_regs()
343 reg_entry++; in rtas_fadump_read_regs()
344 return reg_entry; in rtas_fadump_read_regs()
365 struct rtas_fadump_reg_entry *reg_entry; in rtas_fadump_build_cpu_notes() local
400 if (be64_to_cpu(reg_entry->reg_id) != in rtas_fadump_build_cpu_notes()
407 cpu = (be64_to_cpu(reg_entry->reg_value) & in rtas_fadump_build_cpu_notes()
410 RTAS_FADUMP_SKIP_TO_NEXT_CPU(reg_entry); in rtas_fadump_build_cpu_notes()
417 RTAS_FADUMP_SKIP_TO_NEXT_CPU(reg_entry); in rtas_fadump_build_cpu_notes()
419 reg_entry++; in rtas_fadump_build_cpu_notes()
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/linux-6.15/drivers/gpu/drm/tegra/
H A Drgb.c32 struct reg_entry { struct
37 static const struct reg_entry rgb_enable[] = { argument
59 static const struct reg_entry rgb_disable[] = {
82 const struct reg_entry *table, in tegra_dc_write_regs()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c4342 for (k = 0; k < gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst; k++) { in gfx_v9_4_3_inst_query_ras_err_count()
4345 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) in gfx_v9_4_3_inst_query_ras_err_count()
4349 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), in gfx_v9_4_3_inst_query_ras_err_count()
4358 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), in gfx_v9_4_3_inst_query_ras_err_count()
4375 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) in gfx_v9_4_3_inst_query_ras_err_count()
4379 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), in gfx_v9_4_3_inst_query_ras_err_count()
4413 gfx_v9_4_3_ce_reg_list[i].reg_entry.reg_inst > 1) in gfx_v9_4_3_inst_reset_ras_err_count()
4417 &(gfx_v9_4_3_ce_reg_list[i].reg_entry), in gfx_v9_4_3_inst_reset_ras_err_count()
4422 &(gfx_v9_4_3_ue_reg_list[i].reg_entry), in gfx_v9_4_3_inst_reset_ras_err_count()
4435 gfx_v9_4_3_ue_reg_list[i].reg_entry.reg_inst > 1) in gfx_v9_4_3_inst_reset_ras_err_count()
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H A Damdgpu_ras.h924 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
928 const struct amdgpu_ras_err_status_reg_entry *reg_entry,
H A Damdgpu_ras.c4814 const struct amdgpu_ras_err_status_reg_entry *reg_entry, in amdgpu_ras_inst_get_memory_id_field() argument
4820 if (!reg_entry) in amdgpu_ras_inst_get_memory_id_field()
4824 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, in amdgpu_ras_inst_get_memory_id_field()
4825 reg_entry->seg_lo, reg_entry->reg_lo); in amdgpu_ras_inst_get_memory_id_field()
4828 if ((reg_entry->flags & AMDGPU_RAS_ERR_STATUS_VALID) && in amdgpu_ras_inst_get_memory_id_field()
4838 const struct amdgpu_ras_err_status_reg_entry *reg_entry, in amdgpu_ras_inst_get_err_cnt_field() argument
4844 if (!reg_entry) in amdgpu_ras_inst_get_err_cnt_field()
4848 AMDGPU_RAS_REG_ENTRY_OFFSET(reg_entry->hwip, instance, in amdgpu_ras_inst_get_err_cnt_field()
4849 reg_entry->seg_hi, reg_entry->reg_hi); in amdgpu_ras_inst_get_err_cnt_field()
4852 if ((reg_entry->flags & AMDGPU_RAS_ERR_INFO_VALID) && in amdgpu_ras_inst_get_err_cnt_field()
H A Damdgpu_gfx.h490 struct amdgpu_ras_err_status_reg_entry reg_entry; member