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Searched refs:reg_access_ctrl (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_virt.c1050 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in amdgpu_virt_rlcg_reg_rw() local
1075 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[xcc_id]; in amdgpu_virt_rlcg_reg_rw()
1076 scratch_reg0 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg0; in amdgpu_virt_rlcg_reg_rw()
1077 scratch_reg1 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg1; in amdgpu_virt_rlcg_reg_rw()
1078 scratch_reg2 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg2; in amdgpu_virt_rlcg_reg_rw()
1079 scratch_reg3 = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->scratch_reg3; in amdgpu_virt_rlcg_reg_rw()
1083 if (reg_access_ctrl->spare_int) in amdgpu_virt_rlcg_reg_rw()
1084 spare_int = (void __iomem *)adev->rmmio + 4 * reg_access_ctrl->spare_int; in amdgpu_virt_rlcg_reg_rw()
1086 if (offset == reg_access_ctrl->grbm_cntl) { in amdgpu_virt_rlcg_reg_rw()
1091 } else if (offset == reg_access_ctrl->grbm_idx) { in amdgpu_virt_rlcg_reg_rw()
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H A Damdgpu_rlc.h336 struct amdgpu_rlcg_reg_access_ctrl reg_access_ctrl[AMDGPU_MAX_RLC_INSTANCES]; member
H A Dgfx_v9_4_3.c1390 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v9_4_3_init_rlcg_reg_access_ctrl() local
1394 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1395 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG0); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1396 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG1); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1397 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG2); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1398 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regSCRATCH_REG3); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1399 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1400 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
1401 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPARE_INT); in gfx_v9_4_3_init_rlcg_reg_access_ctrl()
H A Dgfx_v12_0.c714 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v12_0_init_rlcg_reg_access_ctrl() local
716 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v12_0_init_rlcg_reg_access_ctrl()
717 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v12_0_init_rlcg_reg_access_ctrl()
718 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); in gfx_v12_0_init_rlcg_reg_access_ctrl()
719 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v12_0_init_rlcg_reg_access_ctrl()
720 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); in gfx_v12_0_init_rlcg_reg_access_ctrl()
721 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v12_0_init_rlcg_reg_access_ctrl()
722 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v12_0_init_rlcg_reg_access_ctrl()
723 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v12_0_init_rlcg_reg_access_ctrl()
H A Dgfx_v11_0.c896 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v11_0_init_rlcg_reg_access_ctrl() local
898 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v11_0_init_rlcg_reg_access_ctrl()
899 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
900 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1); in gfx_v11_0_init_rlcg_reg_access_ctrl()
901 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2); in gfx_v11_0_init_rlcg_reg_access_ctrl()
902 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3); in gfx_v11_0_init_rlcg_reg_access_ctrl()
903 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL); in gfx_v11_0_init_rlcg_reg_access_ctrl()
904 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX); in gfx_v11_0_init_rlcg_reg_access_ctrl()
905 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0); in gfx_v11_0_init_rlcg_reg_access_ctrl()
H A Dgfx_v9_0.c1822 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v9_0_init_rlcg_reg_access_ctrl() local
1824 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v9_0_init_rlcg_reg_access_ctrl()
1825 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1826 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1827 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1828 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1829 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1830 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); in gfx_v9_0_init_rlcg_reg_access_ctrl()
1831 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT); in gfx_v9_0_init_rlcg_reg_access_ctrl()
H A Dgfx_v10_0.c4359 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; in gfx_v10_0_init_rlcg_reg_access_ctrl() local
4361 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0]; in gfx_v10_0_init_rlcg_reg_access_ctrl()
4362 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4363 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4364 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4365 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4366 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4367 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); in gfx_v10_0_init_rlcg_reg_access_ctrl()
4370 reg_access_ctrl->spare_int = in gfx_v10_0_init_rlcg_reg_access_ctrl()
4374 reg_access_ctrl->spare_int = in gfx_v10_0_init_rlcg_reg_access_ctrl()