Searched refs:rcg (Results 1 – 6 of 6) sorted by relevance
| /linux-6.15/drivers/clk/qcom/ |
| H A D | clk-rcg.c | 44 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_get_parent()
99 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_set_parent()
101 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns); in clk_rcg_set_parent()
246 if (rcg->ns_reg[0] != rcg->ns_reg[1]) { in configure_bank()
348 regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_recalc_rate()
352 regmap_read(rcg->clkr.regmap, rcg->md_reg, &md); in clk_rcg_recalc_rate()
356 if (rcg->clkr.enable_reg != rcg->ns_reg) in clk_rcg_recalc_rate()
388 if (rcg->ns_reg[0] != rcg->ns_reg[1]) in clk_dyn_rcg_recalc_rate()
496 if (rcg->clkr.enable_reg != rcg->ns_reg) { in __clk_rcg_set_rate()
509 regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns); in __clk_rcg_set_rate()
[all …]
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| H A D | clk-rcg2.c | 49 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG) argument
50 #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG) argument
51 #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG) argument
52 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG) argument
201 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); in __clk_rcg2_recalc_rate()
203 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n); in __clk_rcg2_recalc_rate()
1283 struct clk_rcg2 *rcg = &cgfx->rcg; in clk_gfx3d_set_rate_and_parent() local
1436 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, rcg->parked_cfg); in clk_rcg2_shared_enable()
1455 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg); in clk_rcg2_shared_disable()
1577 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg); in clk_rcg2_shared_no_init_park()
[all …]
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| H A D | clk-rcg.h | 184 struct clk_rcg2 rcg; member
189 container_of(to_clk_rcg2(_hw), struct clk_rcg2_gfx3d, rcg)
207 struct clk_rcg2 *rcg; member
212 { .rcg = &r, .init = &r##_init }
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| H A D | gpucc-sdm660.c | 105 .rcg = {
136 &gfx3d_clk_src.rcg.clkr.hw,
273 [GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,
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| H A D | Makefile | 8 clk-qcom-y += clk-rcg.o
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| H A D | mmcc-msm8996.c | 563 .rcg = {
1682 &gfx3d_clk_src.rcg.clkr.hw
3352 [GFX3D_CLK_SRC] = &gfx3d_clk_src.rcg.clkr,
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