clk: qcom: Add NSS clock Controller driver for IPQ9574

Add Networking Sub System Clock Controller (NSSCC) driver for ipq9574 based
devices.

Reviewed-by: Konrad Dybcio <[email protected]

clk: qcom: Add NSS clock Controller driver for IPQ9574

Add Networking Sub System Clock Controller (NSSCC) driver for ipq9574 based
devices.

Reviewed-by: Konrad Dybcio <[email protected]>
Signed-off-by: Devi Priya <[email protected]>
Signed-off-by: Manikanta Mylavarapu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add SM6115 LPASSCC

SM6115 (and its derivatives or similar SoCs) has an LPASS clock
controller block which provides audio-related resets.

Add the required code to support them.

[alexey.k

clk: qcom: Add SM6115 LPASSCC

SM6115 (and its derivatives or similar SoCs) has an LPASS clock
controller block which provides audio-related resets.

Add the required code to support them.

[alexey.klimov] fixed compilation errors after rebase,
slightly changed the commit message

Cc: Konrad Dybcio <[email protected]>
Cc: Konrad Dybcio <[email protected]>
Cc: Srinivas Kandagatla <[email protected]>
Signed-off-by: Konrad Dybcio <[email protected]>
Signed-off-by: Alexey Klimov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add CMN PLL clock controller driver for IPQ SoC

The CMN PLL clock controller supplies clocks to the hardware
blocks that together make up the Ethernet function on Qualcomm
IPQ SoCs and to

clk: qcom: Add CMN PLL clock controller driver for IPQ SoC

The CMN PLL clock controller supplies clocks to the hardware
blocks that together make up the Ethernet function on Qualcomm
IPQ SoCs and to GCC. The driver is initially supported for
IPQ9574 SoC.

The CMN PLL clock controller expects a reference input clock
from the on-board Wi-Fi block acting as clock source. The input
reference clock needs to be configured to one of the supported
clock rates.

The controller supplies a number of fixed-rate output clocks.
For the IPQ9574, there is one output clock of 353 MHZ to PPE
(Packet Process Engine) hardware block, three 50 MHZ output
clocks and an additional 25 MHZ output clock supplied to the
connected Ethernet devices. The PLL also supplies a 24 MHZ
clock as XO and a 32 KHZ sleep clock to GCC, and one 31.25
MHZ clock to PCS.

Signed-off-by: Luo Jie <[email protected]>
Acked-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller

Add driver for Display clock controller (DISPCC) in Qualcomm SM8750.
The device has several differences against SM8650, including new Po

clk: qcom: dispcc-sm8750: Add SM8750 Display clock controller

Add driver for Display clock controller (DISPCC) in Qualcomm SM8750.
The device has several differences against SM8650, including new Pongo
PLLs and different clock parents, thus no compatibility or driver
re-usage.

Signed-off-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add TCSR clock driver for SM8750

The TCSR clock controller found on SM8750 provides refclks
for PCIE, USB and UFS. Add clock driver for it.

Signed-off-by: Melody Olvera <quic_molvera@qui

clk: qcom: Add TCSR clock driver for SM8750

The TCSR clock controller found on SM8750 provides refclks
for PCIE, USB and UFS. Add clock driver for it.

Signed-off-by: Melody Olvera <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add support for GCC on SM8750

Add support for GCC for SM8750 platform.

Signed-off-by: Melody Olvera <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
Reviewed-

clk: qcom: Add support for GCC on SM8750

Add support for GCC for SM8750 platform.

Signed-off-by: Melody Olvera <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: gcc: Add support for QCS615 GCC clocks

Add the global clock controller support for QCS615 SoC.

Signed-off-by: Taniya Das <[email protected]>
Reviewed-by: Imran Shaik <quic_imrashai@q

clk: qcom: gcc: Add support for QCS615 GCC clocks

Add the global clock controller support for QCS615 SoC.

Signed-off-by: Taniya Das <[email protected]>
Reviewed-by: Imran Shaik <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add X1P42100 GPUCC driver

The 8-core X1s have a different GPU subsystem compared to their bigger
cousins, including the clocks part. Add the GPU clock controller driver
to drive these.

S

clk: qcom: Add X1P42100 GPUCC driver

The 8-core X1s have a different GPU subsystem compared to their bigger
cousins, including the clocks part. Add the GPU clock controller driver
to drive these.

Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add support for Global Clock Controller on QCS8300

Add support for Global Clock Controller on QCS8300 platform.

Signed-off-by: Imran Shaik <[email protected]>
Reviewed-by: Taniya

clk: qcom: Add support for Global Clock Controller on QCS8300

Add support for Global Clock Controller on QCS8300 platform.

Signed-off-by: Imran Shaik <[email protected]>
Reviewed-by: Taniya Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC

Add support for the global clock controller found on IPQ5424 SoC.

Reviewed-by: Dmitry Baryshkov <[email protected]>
Co-

clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC

Add support for the global clock controller found on IPQ5424 SoC.

Reviewed-by: Dmitry Baryshkov <[email protected]>
Co-developed-by: Varadarajan Narayanan <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
Signed-off-by: Sricharan Ramabadhran <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: add SAR2130P GPU Clock Controller support

Add support for the GPU Clock Controller as used on the SAR2130P and
SAR1130P platforms.

Signed-off-by: Konrad Dybcio <[email protected]>

clk: qcom: add SAR2130P GPU Clock Controller support

Add support for the GPU Clock Controller as used on the SAR2130P and
SAR1130P platforms.

Signed-off-by: Konrad Dybcio <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: add support for GCC on SAR2130P

Add driver for the Global Clock Controller as present on the Qualcomm
SAR2130P platform. This is based on the msm-5.10 tree, tag
KERNEL.PLATFORM.1.0.r4-004

clk: qcom: add support for GCC on SAR2130P

Add driver for the Global Clock Controller as present on the Qualcomm
SAR2130P platform. This is based on the msm-5.10 tree, tag
KERNEL.PLATFORM.1.0.r4-00400-NEO.0.

Co-developed-by: Kalpak Kawadkar <[email protected]>
Signed-off-by: Kalpak Kawadkar <[email protected]>
Acked-by: Konrad Dybcio <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add support for Display clock Controllers on SA8775P

Add support for display0 and display1 clock controllers on SA8775P
platform.

Reviewed-by: Jagadeesh Kona <[email protected]>
Sig

clk: qcom: Add support for Display clock Controllers on SA8775P

Add support for display0 and display1 clock controllers on SA8775P
platform.

Reviewed-by: Jagadeesh Kona <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-6-4a9f17dc683a@quicinc.com
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add support for Camera Clock Controller on SA8775P

Add support for Camera Clock Controller on SA8755P platform.

Reviewed-by: Jagadeesh Kona <[email protected]>
Signed-off-by: Taniya

clk: qcom: Add support for Camera Clock Controller on SA8775P

Add support for Camera Clock Controller on SA8755P platform.

Reviewed-by: Jagadeesh Kona <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-4-4a9f17dc683a@quicinc.com
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add support for Video clock controller on SA8775P

Add support for Video Clock Controller for SA8775P platform.

Reviewed-by: Jagadeesh Kona <[email protected]>
Signed-off-by: Taniya

clk: qcom: Add support for Video clock controller on SA8775P

Add support for Video Clock Controller for SA8775P platform.

Reviewed-by: Jagadeesh Kona <[email protected]>
Signed-off-by: Taniya Das <[email protected]>
Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-2-4a9f17dc683a@quicinc.com
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add GPUCC driver support for SM4450

Add Graphics Clock Controller (GPUCC) support for SM4450 platform.

Signed-off-by: Ajit Pandey <[email protected]>
Reviewed-by: Konrad Dybcio <ko

clk: qcom: Add GPUCC driver support for SM4450

Add Graphics Clock Controller (GPUCC) support for SM4450 platform.

Signed-off-by: Ajit Pandey <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add CAMCC driver support for SM4450

Add Camera Clock Controller (CAMCC) support for SM4450 platform.

Signed-off-by: Ajit Pandey <[email protected]>
Reviewed-by: Dmitry Baryshkov <d

clk: qcom: Add CAMCC driver support for SM4450

Add Camera Clock Controller (CAMCC) support for SM4450 platform.

Signed-off-by: Ajit Pandey <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add DISPCC driver support for SM4450

Add Display Clock Controller (DISPCC) support for SM4450 platform.

Signed-off-by: Ajit Pandey <[email protected]>
Reviewed-by: Dmitry Baryshkov

clk: qcom: Add DISPCC driver support for SM4450

Add Display Clock Controller (DISPCC) support for SM4450 platform.

Signed-off-by: Ajit Pandey <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: fold dispcc-sm8650 info dispcc-sm8550

There is a very minor difference between display clock controller
drivers for SM8550 and SM8650 platforms. Fold the second one into the
first one to

clk: qcom: fold dispcc-sm8650 info dispcc-sm8550

There is a very minor difference between display clock controller
drivers for SM8550 and SM8650 platforms. Fold the second one into the
first one to reduce kernel footprint. The bindings for these two
hardware blocks are fully compatible.

Signed-off-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add camera clock controller driver for SM8150

Add support for the camera clock controller for camera clients
to be able to request for camcc clocks on SM8150 platform.

Reviewed-by: Bryan

clk: qcom: Add camera clock controller driver for SM8150

Add support for the camera clock controller for camera clients
to be able to request for camcc clocks on SM8150 platform.

Reviewed-by: Bryan O'Donoghue <[email protected]>
Signed-off-by: Satya Priya Kakitapalli <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver

Add support for the camera clock controller for camera clients to
be able to request for camcc clocks on SM8650 platform.

Signed-o

clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver

Add support for the camera clock controller for camera clients to
be able to request for camcc clocks on SM8650 platform.

Signed-off-by: Jagadeesh Kona <[email protected]>
Reviewed-by: Bryan O'Donoghue <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Vladimir Zapolskiy <[email protected]>
Tested-by: Vladimir Zapolskiy <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add QCM2290 GPU clock controller driver

Add a driver for the GPU clock controller block found on the QCM2290 SoC.

Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-b

clk: qcom: Add QCM2290 GPU clock controller driver

Add a driver for the GPU clock controller block found on the QCM2290 SoC.

Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: add clock controller driver for qca8386/qca8084

The clock controller driver of qca8386/qca8084 is registered
as the MDIO device, the hardware register is accessed by MDIO bus
that is norm

clk: qcom: add clock controller driver for qca8386/qca8084

The clock controller driver of qca8386/qca8084 is registered
as the MDIO device, the hardware register is accessed by MDIO bus
that is normally used to access general PHY device, which is
different from the current existed qcom clock controller drivers
using ioremap to access hardware clock registers, nsscc-qca8k is
accessed via an MDIO bus.

MDIO bus is commonly utilized by both qca8386/qca8084 and other
PHY devices, so the mutex lock mdio_bus->mdio_lock should be
used instead of using the mutex lock of remap.

To access the hardware clock registers of qca8386/qca8084, there
is a special MDIO frame sequence, which needs to be sent to the
device.

Enable the reference clock before resetting the clock controller,
the reference clock rate is fixed to 50MHZ.

Reviewed-by: Bryan O'Donoghue <[email protected]>
Signed-off-by: Luo Jie <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add Video Clock Controller driver for SM7150

Add support for the video clock controller found on SM7150.

Signed-off-by: Danila Tikhonov <[email protected]>
Link: https://lore.kernel.org

clk: qcom: Add Video Clock Controller driver for SM7150

Add support for the video clock controller found on SM7150.

Signed-off-by: Danila Tikhonov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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clk: qcom: Add Camera Clock Controller driver for SM7150

Add support for the camera clock controller found on SM7150.

Signed-off-by: Danila Tikhonov <[email protected]>
Link: https://lore.kernel.o

clk: qcom: Add Camera Clock Controller driver for SM7150

Add support for the camera clock controller found on SM7150.

Signed-off-by: Danila Tikhonov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>

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