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Searched refs:phydev_err (Results 1 – 25 of 27) sorted by relevance

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/linux-6.15/drivers/net/phy/aquantia/
H A Daquantia_firmware.c164 phydev_err(phydev, "bad firmware CRC in firmware\n"); in aqr_fw_boot()
177 phydev_err(phydev, "bad primary offset in firmware\n"); in aqr_fw_boot()
187 phydev_err(phydev, "bad fw_header in firmware\n"); in aqr_fw_boot()
196 phydev_err(phydev, "bad iram offset in firmware\n"); in aqr_fw_boot()
203 phydev_err(phydev, "invalid iram size in firmware\n"); in aqr_fw_boot()
210 phydev_err(phydev, "bad dram offset in firmware\n"); in aqr_fw_boot()
217 phydev_err(phydev, "invalid dram size in firmware\n"); in aqr_fw_boot()
249 phydev_err(phydev, "invalid version in firmware\n"); in aqr_fw_boot()
255 phydev_err(phydev, "invalid version in firmware\n"); in aqr_fw_boot()
315 phydev_err(phydev, "firmware loading failed: %d\n", ret); in aqr_firmware_load_nvmem()
[all …]
H A Daquantia_main.c159 phydev_err(phydev, "Reading HW Statistics failed for %s\n", in aqr107_get_stats()
761 phydev_err(phydev, "Failed to read VEND1_GLOBAL_FW_ID: %pe\n", in aqr_wait_reset_complete()
942 phydev_err(phydev, "timeout: processor-intensive MDIO operation\n"); in aqr107_wait_processor_intensive_op()
/linux-6.15/drivers/net/phy/
H A Dair_en8811h.c246 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, in air_buckpbus_reg_write()
296 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, in air_buckpbus_reg_read()
372 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, in air_buckpbus_reg_modify()
426 phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__, in air_write_buf()
443 phydev_err(phydev, "MCU not ready: 0x%x\n", reg_value); in en8811h_wait_mcu_ready()
508 phydev_err(phydev, "Load firmware failed: %d\n", ret); in en8811h_load_firmware()
780 phydev_err(phydev, "LED mode %d is not supported\n", mode); in air_leds_init()
787 phydev_err(phydev, "LED%d init failed: %d\n", i, ret); in air_leds_init()
837 phydev_err(phydev, "Failed to disable leds: %d\n", ret); in en8811h_probe()
907 phydev_err(phydev, "Failed to initialize leds: %d\n", ret); in en8811h_config_init()
H A Ddp83867.c461 phydev_err(phydev, in dp83867_set_downshift()
536 phydev_err(phydev, "ti,rx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
544 phydev_err(phydev, "ti,tx-internal-delay must be specified\n"); in dp83867_verify_rgmii_cfg()
589 phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n"); in dp83867_of_init_io_impedance()
618 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n", in dp83867_of_init()
638 phydev_err(phydev, in dp83867_of_init()
648 phydev_err(phydev, in dp83867_of_init()
671 phydev_err(phydev, "tx-fifo-depth value %u out of range\n", in dp83867_of_init()
682 phydev_err(phydev, "rx-fifo-depth value %u out of range\n", in dp83867_of_init()
H A Ddp83869.c364 phydev_err(phydev, "Failed to read RX CFG\n"); in dp83869_get_wol()
381 phydev_err(phydev, "Failed to read RX SOP 1\n"); in dp83869_get_wol()
391 phydev_err(phydev, "Failed to read RX SOP 2\n"); in dp83869_get_wol()
401 phydev_err(phydev, "Failed to read RX SOP 3\n"); in dp83869_get_wol()
473 phydev_err(phydev, in dp83869_set_downshift()
714 phydev_err(phydev, "selected op-mode is not valid with MII mode\n"); in dp83869_configure_mode()
H A Dnxp-c45-tja11xx.c321 phydev_err(phydev, "Trying to read a reg field of size 0.\n"); in nxp_c45_read_reg_field()
346 phydev_err(phydev, "Trying to write a reg field of size 0.\n"); in nxp_c45_write_reg_field()
1411 phydev_err(phydev, "delay value higher than %u\n", MAX_ID_PS); in nxp_c45_check_delay()
1500 phydev_err(phydev, in nxp_c45_get_delays()
1516 phydev_err(phydev, in nxp_c45_get_delays()
1537 phydev_err(phydev, "rgmii mode not supported\n"); in nxp_c45_set_phy_mode()
1561 phydev_err(phydev, "mii mode not supported\n"); in nxp_c45_set_phy_mode()
1569 phydev_err(phydev, "rev-mii mode not supported\n"); in nxp_c45_set_phy_mode()
1577 phydev_err(phydev, "rmii mode not supported\n"); in nxp_c45_set_phy_mode()
1592 phydev_err(phydev, "sgmii mode not supported\n"); in nxp_c45_set_phy_mode()
[all …]
H A Ddp83822.c645 phydev_err(phydev, "Invalid value for ti,rmii-mode property (%s)\n", in dp8382x_config_rmii_mode()
775 phydev_err(phydev, "LED_0 and COL(GPIO2) cannot be used as LED output at the same time\n"); in dp83822_of_init_leds()
781 phydev_err(phydev, "COL(GPIO2) cannot be used as LED output, already used as clock output\n"); in dp83822_of_init_leds()
787 phydev_err(phydev, "RX_D3 can only be used as LED output when in RMII mode\n"); in dp83822_of_init_leds()
827 phydev_err(phydev, in dp83822_of_init()
848 phydev_err(phydev, in dp83822_of_init()
H A Dcortina.c68 phydev_err(phydev, "Error matching phy with %s driver\n", in cortina_probe()
H A Drockchip.c116 phydev_err(phydev, "rockchip_integrated_phy_analog_init err: %d.\n", in rockchip_link_change_notify()
H A Dphy_device.c647 phydev_err(dev, "error %d loading PHY driver module for ID 0x%08lx\n", in phy_request_driver_module()
1023 phydev_err(phydev, "failed to initialize\n"); in phy_device_register()
1029 phydev_err(phydev, "failed to add\n"); in phy_device_register()
1507 phydev_err(phydev, "failed to get the bus module\n"); in phy_attach_direct()
1526 phydev_err(phydev, "failed to get the device driver module\n"); in phy_attach_direct()
1575 phydev_err(phydev, "error creating 'phy_standalone' sysfs entry\n"); in phy_attach_direct()
2301 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); in genphy_read_lpa()
2303 phydev_err(phydev, "Master/Slave resolution failed\n"); in genphy_read_lpa()
2925 phydev_err(phydev, "Delay %d is out of range\n", delay); in phy_get_internal_delay()
2947 phydev_err(phydev, "error finding internal delay index for %d\n", in phy_get_internal_delay()
H A Dmxl-gpy.c366 phydev_err(phydev, "Error: MDIO register access failed: %d\n", in gpy_2500basex_chk()
388 phydev_err(phydev, "Error: MMD register access failed: %d\n", in gpy_sgmii_aneg_en()
554 phydev_err(phydev, in gpy_update_interface()
573 phydev_err(phydev, in gpy_update_interface()
H A Dmotorcomm.c1221 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); in ytphy_utp_read_lpa()
1223 phydev_err(phydev, "Master/Slave resolution failed\n"); in ytphy_utp_read_lpa()
2397 phydev_err(phydev, "Failed to select page: %d\n", in yt8821_serdes_init()
2432 phydev_err(phydev, "Failed to select page: %d\n", in yt8821_utp_init()
2623 phydev_err(phydev, "Failed to select page: %d\n", in yt8821_auto_sleep_config()
H A Dmicrochip.c359 phydev_err(phydev, "Link change process failed %pe\n", ERR_PTR(ret)); in lan88xx_link_change_notify()
H A Dmicrochip_t1s.c294 phydev_err(phydev, "PHY reset failed\n"); in lan867x_check_reset_complete()
H A Dadin.c514 phydev_err(phydev, "invalid adi,phy-output-clock\n"); in adin_config_clk_out()
621 phydev_err(phydev, in adin_cl45_to_adin_reg()
H A Dmicrel.c623 phydev_err(phydev, "failed to set led mode\n"); in kszphy_setup_led()
642 phydev_err(phydev, "failed to disable broadcast address\n"); in kszphy_broadcast_disable()
662 phydev_err(phydev, "failed to disable NAND tree mode\n"); in kszphy_nand_tree_disable()
676 phydev_err(phydev, in kszphy_config_reset()
1279 phydev_err(phydev, "failed to force the phy to master mode\n"); in ksz9031_config_init()
2141 phydev_err(phydev, "invalid led mode: 0x%02x\n", in kszphy_parse_led_mode()
2302 phydev_err(phydev, "Clock rate out of range: %ld\n", in kszphy_probe()
2603 phydev_err(phydev, "Error: phy_write has returned error %d\n", in lanphy_write_page_reg()
3927 phydev_err(phydev, "ptp_clock_register failed %lu\n", in lan8814_ptp_probe_once()
5358 phydev_err(phydev, "ptp_clock_register failed: %lu\n", in lan8841_probe()
H A Dphy.c534 phydev_err(phydev, "Error while aborting cable test"); in phy_abort_cable_test()
1340 phydev_err(phydev, "PHY-device data unsafe context\n"); in phy_process_error()
H A Dmicrochip_rds_ptp.c955 phydev_err(phydev, "RX Timestamp is not valid!\n"); in mchp_rds_ptp_get_rx_ts()
H A Dmarvell10g.c840 phydev_err(phydev, "MACTYPE configuration invalid\n"); in mv3310_config_init()
/linux-6.15/drivers/net/phy/qcom/
H A Dat803x.c255 phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n"); in at803x_parse_dt()
263 phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n"); in at803x_parse_dt()
285 phydev_err(phydev, "invalid qca,clk-out-frequency\n"); in at803x_parse_dt()
307 phydev_err(phydev, "invalid qca,clk-out-strength\n"); in at803x_parse_dt()
712 phydev_err(phydev, "failed to register VDDIO regulator\n"); in at8031_register_regulators()
718 phydev_err(phydev, "failed to register VDDH regulator\n"); in at8031_register_regulators()
793 phydev_err(phydev, "failed to get VDDIO regulator\n"); in at8031_parse_dt()
H A Dqca808x.c612 phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n"); in qca808x_led_polarity_set()
/linux-6.15/drivers/net/phy/mediatek/
H A Dmtk-ge-soc.c398 phydev_err(phydev, "Calibration cycle timeout\n"); in cal_cycle()
1143 phydev_err(phydev, "cal %d failed\n", cal_item); in start_cal()
1170 phydev_err(phydev, "invalid efuse data\n"); in mt798x_phy_calibration()
/linux-6.15/include/linux/
H A Dphy.h1336 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \
1436 phydev_err(phydev, "%s failed: %d\n", __func__, __ret); \
1877 #define phydev_err(_phydev, format, args...) \ macro
/linux-6.15/net/ethtool/
H A Dcabletest.c52 phydev_err(phydev, "%s: Error %pe\n", __func__, ERR_PTR(err)); in ethnl_cable_test_started()
/linux-6.15/drivers/net/phy/mscc/
H A Dmscc_main.c265 phydev_err(phydev, "Downshift count should be 2,3,4 or 5\n"); in vsc85xx_downshift_set()
424 phydev_err(phydev, "DT %s invalid\n", led); in vsc85xx_dt_led_mode_get()

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