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Searched refs:num_instances (Results 1 – 25 of 44) sorted by relevance

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/linux-6.15/drivers/accel/habanalabs/common/
H A Dsecurity.c327 for (j = 0 ; j < num_instances ; j++) { in hl_init_pb_with_mask()
328 int seq = i * num_instances + j; in hl_init_pb_with_mask()
360 u32 num_instances, u32 instance_offset, in hl_init_pb() argument
411 for (j = 0 ; j < num_instances ; j++) { in hl_init_pb_ranges_with_mask()
412 int seq = i * num_instances + j; in hl_init_pb_ranges_with_mask()
472 u32 num_instances, u32 instance_offset, in hl_init_pb_single_dcore() argument
492 for (i = 0 ; i < num_instances ; i++) in hl_init_pb_single_dcore()
520 u32 num_instances, u32 instance_offset, in hl_init_pb_ranges_single_dcore() argument
539 for (i = 0 ; i < num_instances ; i++) in hl_init_pb_ranges_single_dcore()
572 int seq = i * num_instances + j; in hl_ack_pb_with_mask()
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H A Dhabanalabs.h4203 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4207 u32 num_instances, u32 instance_offset,
4211 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4216 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4221 u32 num_instances, u32 instance_offset,
4225 u32 num_instances, u32 instance_offset,
4230 u32 num_instances, u32 instance_offset,
4233 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4236 u32 num_instances, u32 instance_offset,
/linux-6.15/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-nvidia.c37 unsigned int num_instances; member
69 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_write_reg()
90 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_write_reg64()
112 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_tlb_sync()
137 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_reset()
182 for (inst = 0; inst < nvidia->num_instances; inst++) { in nvidia_smmu_global_fault()
230 for (inst = 0; inst < nvidia->num_instances; inst++) { in nvidia_smmu_context_fault()
323 nvidia_smmu->num_instances++; in nvidia_smmu_impl_init()
334 nvidia_smmu->num_instances++; in nvidia_smmu_impl_init()
337 if (nvidia_smmu->num_instances == 1) in nvidia_smmu_impl_init()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_sdma.c43 for (i = 0; i < adev->sdma.num_instances; i++) in amdgpu_sdma_get_instance_from_ring()
56 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_get_index_from_ring()
109 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_ras_late_init()
199 for (i = 0; i < adev->sdma.num_instances; i++) { in amdgpu_sdma_destroy_inst_ctx()
246 for (i = 1; i < adev->sdma.num_instances; i++) in amdgpu_sdma_init_microcode()
382 for (i = 0; i < adev->sdma.num_instances; ++i) { in amdgpu_debugfs_sdma_sched_mask_set()
421 for (i = 0; i < adev->sdma.num_instances; ++i) { in amdgpu_debugfs_sdma_sched_mask_get()
456 if (!(adev->sdma.num_instances > 1)) in amdgpu_debugfs_sdma_sched_mask_init()
487 if (adev->sdma.num_instances) { in amdgpu_sdma_sysfs_reset_mask_init()
502 if (adev->sdma.num_instances) in amdgpu_sdma_sysfs_reset_mask_fini()
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H A Dsdma_v4_0.c602 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_setup_ulv()
627 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_init_microcode()
927 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_gfx_enable()
961 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_page_stop()
1010 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_ctx_switch_enable()
1056 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_enable()
1349 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_load_microcode()
1405 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_0_start()
2045 if (j == adev->sdma.num_instances) in sdma_v4_0_wait_for_idle()
2527 switch (adev->sdma.num_instances) { in sdma_v4_0_set_irq_funcs()
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H A Dsdma_v3_0.c254 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v3_0_free_microcode()
305 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_init_microcode()
334 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v3_0_init_microcode()
519 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_gfx_stop()
578 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_ctx_switch_enable()
620 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_enable()
647 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_gfx_resume()
745 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v3_0_gfx_resume()
1092 adev->sdma.num_instances = 1; in sdma_v3_0_early_init()
1095 adev->sdma.num_instances = SDMA_MAX_INSTANCE; in sdma_v3_0_early_init()
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H A Dcik_sdma.c77 for (i = 0; i < adev->sdma.num_instances; i++) in cik_sdma_free_microcode()
133 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_init_microcode()
149 for (i = 0; i < adev->sdma.num_instances; i++) in cik_sdma_init_microcode()
314 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_gfx_stop()
371 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_ctx_switch_enable()
409 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_enable()
434 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_gfx_resume()
497 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_gfx_resume()
539 for (i = 0; i < adev->sdma.num_instances; i++) { in cik_sdma_load_microcode()
928 adev->sdma.num_instances = SDMA_MAX_INSTANCE; in cik_sdma_early_init()
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H A Dsdma_v4_4_2.c164 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_inst_init_golden_registers()
193 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_init_microcode()
1445 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_sw_init()
1521 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_sw_fini()
1601 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_is_idle()
1623 if (j == adev->sdma.num_instances) in sdma_v4_4_2_wait_for_idle()
1779 for (i = instance; i < adev->sdma.num_instances; in sdma_v4_4_2_process_trap_irq()
1786 if (i >= adev->sdma.num_instances) { in sdma_v4_4_2_process_trap_irq()
2067 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_print_ip_state()
2087 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_2_dump_ip_state()
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H A Dsi_dma.c118 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_stop()
133 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_start()
464 adev->sdma.num_instances = 2; in si_dma_early_init()
492 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_sw_init()
514 for (i = 0; i < adev->sdma.num_instances; i++) in si_dma_sw_fini()
643 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_set_clockgating_state()
655 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_set_clockgating_state()
736 for (i = 0; i < adev->sdma.num_instances; i++) in si_dma_set_ring_funcs()
830 for (i = 0; i < adev->sdma.num_instances; i++) { in si_dma_set_vm_pte_funcs()
834 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances; in si_dma_set_vm_pte_funcs()
H A Dsdma_v2_4.c114 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v2_4_free_microcode()
145 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_init_microcode()
176 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v2_4_init_microcode()
343 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_gfx_stop()
383 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_enable()
408 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_gfx_resume()
471 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_gfx_resume()
817 adev->sdma.num_instances = SDMA_MAX_INSTANCE; in sdma_v2_4_early_init()
855 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v2_4_sw_init()
876 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v2_4_sw_fini()
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H A Dsdma_v7_0.c430 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_gfx_stop()
485 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_enable()
664 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_gfx_resume()
691 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v12_0_free_ucode_buffer()
728 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_load_microcode()
787 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_soft_reset()
822 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_check_soft_reset()
840 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v7_0_reset_queue()
845 if (i == adev->sdma.num_instances) { in sdma_v7_0_reset_queue()
1389 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v7_0_sw_fini()
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H A Dsdma_v6_0.c399 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_gfx_stop()
435 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_ctxempty_int_enable()
465 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_enable()
635 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_gfx_resume()
767 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_soft_reset()
802 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_check_soft_reset()
1332 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_sw_init()
1391 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v6_0_sw_fini()
1437 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v6_0_is_idle()
1522 if (i == adev->sdma.num_instances) { in sdma_v6_0_reset_queue()
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H A Dsdma_v5_2.c418 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_gfx_stop()
477 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_ctx_switch_enable()
516 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_enable()
698 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_gfx_resume()
738 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_load_microcode()
771 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_soft_reset()
1331 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_sw_init()
1339 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_2_sw_init()
1397 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v5_2_sw_fini()
1486 if (i == adev->sdma.num_instances) { in sdma_v5_2_reset_queue()
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H A Dvpe_v6_1.c78 for (i = 0; i < vpe->num_instances; i++) { in vpe_v6_1_halt()
108 for (i = 0; i < vpe->num_instances; i++) { in vpe_v6_1_set_collaborate_mode()
133 for (j = 0; j < vpe->num_instances; j++) { in vpe_v6_1_load_microcode()
183 for (j = 0; j < vpe->num_instances; j++) { in vpe_v6_1_load_microcode()
215 for (i = 0; i < vpe->num_instances; i++) { in vpe_v6_1_ring_start()
282 for (i = 0; i < vpe->num_instances; i++) { in vpe_v_6_1_ring_stop()
H A Dsdma_v5_0.c292 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_init_microcode()
599 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_stop()
658 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_ctx_switch_enable()
700 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_enable()
882 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_gfx_resume()
922 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_load_microcode()
1433 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_sw_init()
1487 for (i = 0; i < adev->sdma.num_instances; i++) in sdma_v5_0_sw_fini()
1538 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v5_0_is_idle()
1586 if (i == adev->sdma.num_instances) { in sdma_v5_0_reset_queue()
[all …]
H A Dsdma_v4_4.c243 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_reset_ras_error_count()
256 for (i = 0; i < adev->sdma.num_instances; i++) { in sdma_v4_4_query_ras_error_count()
H A Daqua_vanjaram.c51 for (i = 0; i < adev->sdma.num_instances; i++) in aqua_vanjaram_doorbell_index_init()
401 num_sdma = adev->sdma.num_instances; in __aqua_vanjaram_get_xcp_ip_info()
465 max_res[AMDGPU_XCP_RES_DMA] = adev->sdma.num_instances; in aqua_vanjaram_get_xcp_res_info()
815 adev->sdma.num_instances = NUM_SDMA(adev->sdma.sdma_mask); in aqua_vanjaram_init_soc_config()
948 pcie_reg_state->common_header.num_instances = 1; in aqua_vanjaram_read_pcie_state()
1032 xgmi_reg_state->common_header.num_instances = max_xgmi_instances; in aqua_vanjaram_read_xgmi_state()
1105 wafl_reg_state->common_header.num_instances = max_wafl_instances; in aqua_vanjaram_read_wafl_state()
1224 usr_reg_state->common_header.num_instances = max_usr_instances; in aqua_vanjaram_read_usr_state()
H A Damdgpu_vpe.h80 uint32_t num_instances; member
H A Damdgpu_discovery.c1407 if (adev->sdma.num_instances < in amdgpu_discovery_reg_base_init()
1409 adev->sdma.num_instances++; in amdgpu_discovery_reg_base_init()
1414 adev->sdma.num_instances + 1, in amdgpu_discovery_reg_base_init()
1421 adev->vpe.num_instances++; in amdgpu_discovery_reg_base_init()
1424 adev->vpe.num_instances + 1, in amdgpu_discovery_reg_base_init()
2585 adev->sdma.num_instances = 2; in amdgpu_discovery_set_ip_blocks()
2607 adev->sdma.num_instances = 2; in amdgpu_discovery_set_ip_blocks()
2629 adev->sdma.num_instances = 1; in amdgpu_discovery_set_ip_blocks()
2670 adev->sdma.num_instances = 2; in amdgpu_discovery_set_ip_blocks()
2693 adev->sdma.num_instances = 8; in amdgpu_discovery_set_ip_blocks()
[all …]
H A Damdgpu_sdma.h124 int num_instances; member
/linux-6.15/drivers/gpu/drm/amd/include/
H A Damdgpu_reg_state.h51 uint8_t num_instances; member
/linux-6.15/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-lite.h69 unsigned short num_instances; member
/linux-6.15/include/sound/
H A Dtimer.h79 int num_instances; /* current number of timer instances */ member
/linux-6.15/drivers/hwmon/
H A Dibmaem.c191 u8 num_instances; member
203 u8 num_instances; member
519 return ff_resp.num_instances; in aem_find_aem1_count()
657 fi_resp->num_instances <= instance_num) in aem_find_aem2()
/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_device.c133 kfd->adev->sdma.num_instances * in kfd_device_info_set_sdma_info()
1438 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes; in kfd_get_num_sdma_engines()
1440 return min(node->adev->sdma.num_instances/(int)node->kfd->num_nodes, 2); in kfd_get_num_sdma_engines()
1446 return node->adev->sdma.num_instances/(int)node->kfd->num_nodes - in kfd_get_num_xgmi_sdma_engines()

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