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Searched refs:mmSPI_CONFIG_CNTL_1 (Results 1 – 16 of 16) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c136 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
H A Dgfx_v10_0.c487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
3351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
H A Dgfx_v9_0.c690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
H A Dgfx_v6_0.c1743 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); in gfx_v6_0_constants_init()
H A Dgfx_v7_0.c1979 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT)); in gfx_v7_0_constants_init()
H A Dgfx_v8_0.c414 mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h1195 #define mmSPI_CONFIG_CNTL_1 0x244F macro
H A Dgfx_7_0_d.h1478 #define mmSPI_CONFIG_CNTL_1 0x244f macro
H A Dgfx_7_2_d.h1499 #define mmSPI_CONFIG_CNTL_1 0x244f macro
H A Dgfx_8_0_d.h1691 #define mmSPI_CONFIG_CNTL_1 0x244f macro
H A Dgfx_8_1_d.h1659 #define mmSPI_CONFIG_CNTL_1 0x244f macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h5139 #define mmSPI_CONFIG_CNTL_1 … macro
H A Dgc_9_1_offset.h5369 #define mmSPI_CONFIG_CNTL_1 … macro
H A Dgc_9_2_1_offset.h5327 #define mmSPI_CONFIG_CNTL_1 … macro
H A Dgc_10_1_0_offset.h2601 #define mmSPI_CONFIG_CNTL_1 … macro
H A Dgc_10_3_0_offset.h2690 #define mmSPI_CONFIG_CNTL_1 … macro