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Searched refs:mmRLC_CGCG_CGLS_CTRL (Results 1 – 17 of 17) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c83 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
214 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
244 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
H A Dsi.c538 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
637 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
735 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
815 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
895 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
H A Dgfx_v8_0.c206 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
304 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
318 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
349 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
381 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
423 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
467 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
481 mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
5434 data = RREG32(mmRLC_CGCG_CGLS_CTRL); in gfx_v8_0_get_clockgating_state()
5744 WREG32(mmRLC_CGCG_CGLS_CTRL, data); in gfx_v8_0_update_coarse_grain_clock_gating()
[all …]
H A Dgfx_v7_0.c3432 tmp = RREG32(mmRLC_CGCG_CGLS_CTRL) & 0xfffffffc; in gfx_v7_0_rlc_resume()
3433 WREG32(mmRLC_CGCG_CGLS_CTRL, tmp); in gfx_v7_0_rlc_resume()
3491 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); in gfx_v7_0_enable_cgcg()
3512 WREG32(mmRLC_CGCG_CGLS_CTRL, data); in gfx_v7_0_enable_cgcg()
3524 WREG32(mmRLC_CGCG_CGLS_CTRL, data); in gfx_v7_0_enable_cgcg()
H A Dgfx_v9_0.c3179 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); in gfx_v9_0_rlc_resume()
5075 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v9_0_update_coarse_grain_clock_gating()
5087 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v9_0_update_coarse_grain_clock_gating()
5096 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v9_0_update_coarse_grain_clock_gating()
5101 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v9_0_update_coarse_grain_clock_gating()
5291 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); in gfx_v9_0_get_clockgating_state()
H A Dgfx_v6_0.c2544 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL); in gfx_v6_0_enable_cgcg()
2575 WREG32(mmRLC_CGCG_CGLS_CTRL, data); in gfx_v6_0_enable_cgcg()
H A Dgfx_v10_0.c5546 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); in gfx_v10_0_rlc_resume()
8046 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v10_0_update_coarse_grain_clock_gating()
8058 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v10_0_update_coarse_grain_clock_gating()
8067 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL); in gfx_v10_0_update_coarse_grain_clock_gating()
8078 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data); in gfx_v10_0_update_coarse_grain_clock_gating()
8478 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL)); in gfx_v10_0_get_clockgating_state()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h1133 #define mmRLC_CGCG_CGLS_CTRL 0x3101 macro
H A Dgfx_7_0_d.h1281 #define mmRLC_CGCG_CGLS_CTRL 0x3109 macro
H A Dgfx_7_2_d.h1294 #define mmRLC_CGCG_CGLS_CTRL 0x3109 macro
H A Dgfx_8_0_d.h1392 #define mmRLC_CGCG_CGLS_CTRL 0xec49 macro
H A Dgfx_8_1_d.h1394 #define mmRLC_CGCG_CGLS_CTRL 0xec49 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h6045 #define mmRLC_CGCG_CGLS_CTRL … macro
H A Dgc_9_1_offset.h6267 #define mmRLC_CGCG_CGLS_CTRL … macro
H A Dgc_9_2_1_offset.h6243 #define mmRLC_CGCG_CGLS_CTRL … macro
H A Dgc_10_1_0_offset.h9393 #define mmRLC_CGCG_CGLS_CTRL … macro
H A Dgc_10_3_0_offset.h9215 #define mmRLC_CGCG_CGLS_CTRL … macro