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Searched refs:mmGRBM_GFX_INDEX (Results 1 – 25 of 27) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v10_0.c503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3817 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, in gfx_v10_0_kiq_reset_hw_queue()
5042 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in gfx_v10_0_select_se_sh()
7901 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); in gfx_v10_0_update_medium_grain_clock_gating()
[all …]
H A Dvce_v3_0.c85 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_get_rptr()
87 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_get_rptr()
117 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_get_wptr()
119 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_get_wptr()
148 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_ring_set_wptr()
150 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_ring_set_wptr()
275 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx)); in vce_v3_0_start()
648 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_check_soft_reset()
653 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1)); in vce_v3_0_check_soft_reset()
658 WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0)); in vce_v3_0_check_soft_reset()
[all …]
H A Dmxgpu_vi.c50 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
80 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
127 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
135 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
141 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
171 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
270 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
H A Dsi.c429 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
454 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
558 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
583 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
656 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
681 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
756 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
781 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
836 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
861 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
H A Damdgpu_amdkfd_gfx_v7.c504 WREG32(mmGRBM_GFX_INDEX, gfx_index_val); in kgd_wave_control_execute()
513 WREG32(mmGRBM_GFX_INDEX, data); in kgd_wave_control_execute()
H A Damdgpu_amdkfd_gfx_v8.c550 WREG32(mmGRBM_GFX_INDEX, gfx_index_val); in kgd_wave_control_execute()
560 WREG32(mmGRBM_GFX_INDEX, data); in kgd_wave_control_execute()
H A Damdgpu_amdkfd_gfx_v10_3.c597 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val); in wave_control_execute_v10_3()
607 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in wave_control_execute_v10_3()
H A Dgfx_v8_0.c219 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
232 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
261 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
331 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
362 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
393 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
405 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
413 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
435 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
464 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
[all …]
H A Damdgpu_amdkfd_gfx_v10.c685 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val); in kgd_wave_control_execute()
695 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in kgd_wave_control_execute()
H A Damdgpu_amdkfd_gfx_v9.c635 WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, gfx_index_val); in kgd_gfx_v9_wave_control_execute()
645 WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, data); in kgd_gfx_v9_wave_control_execute()
H A Dgfx_v9_4.c116 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); in gfx_v9_4_select_se_sh()
925 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); in gfx_v9_4_reset_ras_error_count()
H A Dgfx_v9_0.c848 {SOC15_REG_ENTRY(GC, 0, mmGRBM_GFX_INDEX)},
1830 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX); in gfx_v9_0_init_rlcg_reg_access_ctrl()
2497 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); in gfx_v9_0_select_se_sh()
7024 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000); in gfx_v9_0_reset_ras_error_count()
H A Dgfx_v6_0.c1323 WREG32(mmGRBM_GFX_INDEX, data); in gfx_v6_0_select_se_sh()
H A Dgfx_v7_0.c1578 WREG32(mmGRBM_GFX_INDEX, data); in gfx_v7_0_select_se_sh()
/linux-6.15/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_powertune.c896 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_cac_driving_se_didt_config()
911 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_cac_driving_se_didt_config()
947 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_psm_gc_didt_config()
956 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_psm_gc_didt_config()
1008 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_se_edc_config()
1019 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_se_edc_config()
1058 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); in vega10_enable_psm_gc_edc_config()
1067 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_psm_gc_edc_config()
1117 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000); in vega10_enable_se_edc_force_stall_config()
H A Dsmu7_powertune.c976 value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX); in smu7_enable_didt_config()
981 cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value); in smu7_enable_didt_config()
1010 cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value2); in smu7_enable_didt_config()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_offset.h229 #define mmGRBM_GFX_INDEX … macro
H A Dgc_9_0_offset.h4913 #define mmGRBM_GFX_INDEX … macro
H A Dgc_9_1_offset.h5143 #define mmGRBM_GFX_INDEX … macro
H A Dgc_9_2_1_offset.h5099 #define mmGRBM_GFX_INDEX … macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h750 #define mmGRBM_GFX_INDEX 0x200B macro
H A Dgfx_7_0_d.h783 #define mmGRBM_GFX_INDEX 0xc200 macro
H A Dgfx_7_2_d.h796 #define mmGRBM_GFX_INDEX 0xc200 macro
H A Dgfx_8_0_d.h871 #define mmGRBM_GFX_INDEX 0xc200 macro
H A Dgfx_8_1_d.h871 #define mmGRBM_GFX_INDEX 0xc200 macro

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