Home
last modified time | relevance | path

Searched refs:max_sh_per_se (Results 1 – 25 of 27) sorted by relevance

12

/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager.c126 if (gfx_info->max_sh_per_se > KFD_MAX_NUM_SH_PER_SE) { in mqd_symmetrically_map_cu_mask()
129 gfx_info->max_sh_per_se * gfx_info->max_shader_engines); in mqd_symmetrically_map_cu_mask()
148 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) in mqd_symmetrically_map_cu_mask()
194 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { in mqd_symmetrically_map_cu_mask()
H A Dkfd_topology.c1686 for (j = 0; j < gfx_info->max_sh_per_se && !found; j++) { in fill_in_l2_l3_pcache()
1743 for (j = 0; j < gfx_info->max_sh_per_se; j++) { in fill_in_l2_l3_pcache()
1811 for (j = 0; j < gfx_info->max_sh_per_se; j++) { in kfd_fill_cache_non_crat_info()
2071 gfx_info->max_sh_per_se; in kfd_topology_add_device()
H A Dkfd_crat.c2286 cu->array_count = gfx_info->max_sh_per_se * in kfd_create_vcrat_image_gpu()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_atomfirmware.c833 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
851 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
872 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
H A Dgfx_v6_0.c1336 adev->gfx.config.max_sh_per_se); in gfx_v6_0_get_rb_active_bitmap()
1470 adev->gfx.config.max_sh_per_se; in gfx_v6_0_setup_rb()
1475 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1479 ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v6_0_setup_rb()
1503 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1551 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_spi()
1589 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1606 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1623 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1640 adev->gfx.config.max_sh_per_se = 1; in gfx_v6_0_constants_init()
[all …]
H A Dgfx_v7_0.c1600 adev->gfx.config.max_sh_per_se); in gfx_v7_0_get_rb_active_bitmap()
1760 adev->gfx.config.max_sh_per_se; in gfx_v7_0_setup_rb()
1765 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1768 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v7_0_setup_rb()
1794 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
3269 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_wait_for_rlc_serdes()
4188 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4205 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4223 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4241 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
[all …]
H A Dgfx_v8_0.c1678 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1695 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1742 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1758 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1775 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1793 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
3449 adev->gfx.config.max_sh_per_se); in gfx_v8_0_get_rb_active_bitmap()
3611 adev->gfx.config.max_sh_per_se; in gfx_v8_0_setup_rb()
3616 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
3645 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
[all …]
H A Damdgpu_debugfs.c130 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
256 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_regs2_op()
898 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
H A Damdgpu_gfx.h194 unsigned max_sh_per_se; member
H A Dgfx_v9_0.c1682 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_init_always_on_cu_mask()
2511 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_rb_active_bitmap()
2522 adev->gfx.config.max_sh_per_se; in gfx_v9_0_setup_rb()
2526 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_setup_rb()
2529 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v9_0_setup_rb()
2695 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_wait_for_rlc_serdes()
4609 adev->gfx.config.max_sh_per_se; in gfx_v9_0_do_edc_gpr_workarounds()
7821 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_0_get_cu_info()
7826 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_cu_info()
7830 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_get_cu_info()
[all …]
H A Dgfxhub_v2_1.c515 adev->gfx.config.max_sh_per_se * in gfxhub_v2_1_utcl2_harvest()
H A Dgfx_v9_4_3.c1423 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_4_3_xcc_wait_for_rlc_serdes()
4842 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_4_3_get_cu_info()
4847 adev->gfx.config.max_sh_per_se); in gfx_v9_4_3_get_cu_info()
4853 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_4_3_get_cu_info()
4860 disable_masks[i * adev->gfx.config.max_sh_per_se + j], in gfx_v9_4_3_get_cu_info()
H A Dgfx_v10_0.c5056 adev->gfx.config.max_sh_per_se); in gfx_v10_0_get_rb_active_bitmap()
5068 adev->gfx.config.max_sh_per_se; in gfx_v10_0_setup_rb()
5072 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_setup_rb()
5073 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_setup_rb()
5084 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v10_0_setup_rb()
5245 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_tcp_harvest()
10004 adev->gfx.config.max_sh_per_se * in gfx_v10_0_set_gds_init()
10093 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_get_cu_info()
10094 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_get_cu_info()
10151 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v10_3_get_disabled_sa()
[all …]
H A Damdgpu_atombios.c748 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; in amdgpu_atombios_get_gfx_info()
H A Dgfx_v9_4_2.c1864 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; in gfx_v9_4_2_query_sq_timeout_status()
1897 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; in gfx_v9_4_2_reset_sq_timeout_status()
H A Dgfx_v12_0.c1625 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v12_0_get_sa_active_bitmap()
1667 adev->gfx.config.max_sh_per_se; in gfx_v12_0_setup_rb()
1669 adev->gfx.config.max_sh_per_se; in gfx_v12_0_setup_rb()
5509 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v12_0_get_cu_info()
5510 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v12_0_get_cu_info()
H A Dgfx_v11_0.c1904 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v11_0_get_sa_active_bitmap()
1946 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()
1948 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()
7041 adev->gfx.config.max_sh_per_se * in gfx_v11_0_set_gds_init()
7125 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v11_0_get_cu_info()
7126 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v11_0_get_cu_info()
H A Damdgpu_discovery.c1592 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
1636 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); in amdgpu_discovery_get_gfx_info()
H A Damdgpu_kms.c861 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in amdgpu_info_ioctl()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dradeon_kms.c459 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()
461 *value = rdev->config.si.max_sh_per_se; in radeon_info_ioctl()
H A Dsi.c3083 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3100 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3118 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3135 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3152 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3269 rdev->config.si.max_sh_per_se, in si_gpu_init()
3273 rdev->config.si.max_sh_per_se, in si_gpu_init()
3278 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_gpu_init()
5309 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_init_ao_cu_mask()
H A Dcik.c3181 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3198 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3216 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3234 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3336 rdev->config.cik.max_sh_per_se, in cik_gpu_init()
3341 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_gpu_init()
5787 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_wait_for_rlc_serdes()
6554 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_init_ao_cu_mask()
H A Dradeon.h2126 unsigned max_sh_per_se; member
2157 unsigned max_sh_per_se; member
/linux-6.15/drivers/gpu/drm/amd/include/
H A Datomfirmware.h1796 uint8_t max_sh_per_se; member
1816 uint8_t max_sh_per_se; member
1841 uint8_t max_sh_per_se; member
1876 uint8_t max_sh_per_se; member
1917 uint8_t max_sh_per_se; member
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dvangogh_ppt.c2225 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; in vangogh_post_smu_init()
2251 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; in vangogh_post_smu_init()

12