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Searched refs:inst_idx (Results 1 – 17 of 17) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c441 int inst_idx = vinst->inst; in vcn_v5_0_0_mc_resume_dpg_mode() local
477 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), in vcn_v5_0_0_mc_resume_dpg_mode()
531 VCN, inst_idx, regUVD_VCPU_NONCACHE_SIZE0), in vcn_v5_0_0_mc_resume_dpg_mode()
536 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), in vcn_v5_0_0_mc_resume_dpg_mode()
711 int inst_idx = vinst->inst; in vcn_v5_0_0_start_dpg_mode() local
727 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v5_0_0_start_dpg_mode()
765 VCN, inst_idx, regUVD_MASTINT_EN), in vcn_v5_0_0_start_dpg_mode()
769 amdgpu_vcn_psp_update_sram(adev, inst_idx, 0); in vcn_v5_0_0_start_dpg_mode()
771 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; in vcn_v5_0_0_start_dpg_mode()
962 int inst_idx = vinst->inst; in vcn_v5_0_0_stop_dpg_mode() local
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H A Dvcn_v4_0_5.c463 int inst_idx = vinst->inst; in vcn_v4_0_5_mc_resume_dpg_mode() local
563 VCN, inst_idx, regUVD_GFX10_ADDR_CONFIG), in vcn_v4_0_5_mc_resume_dpg_mode()
796 int inst_idx = vinst->inst; in vcn_v4_0_5_disable_clock_gating_dpg_mode() local
913 int inst_idx = vinst->inst; in vcn_v4_0_5_start_dpg_mode() local
957 VCN, inst_idx, regUVD_MPC_CNTL), in vcn_v4_0_5_start_dpg_mode()
961 VCN, inst_idx, regUVD_MPC_SET_MUXA0), in vcn_v4_0_5_start_dpg_mode()
968 VCN, inst_idx, regUVD_MPC_SET_MUXB0), in vcn_v4_0_5_start_dpg_mode()
975 VCN, inst_idx, regUVD_MPC_SET_MUX), in vcn_v4_0_5_start_dpg_mode()
994 VCN, inst_idx, regUVD_MASTINT_EN), in vcn_v4_0_5_start_dpg_mode()
1229 int inst_idx = vinst->inst; in vcn_v4_0_5_stop_dpg_mode() local
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H A Damdgpu_jpeg.h39 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
42 JPEG, GET_INST(JPEG, inst_idx), \
48 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
50 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
57 WREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_CTL, \
66 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
68 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
71 JPEG, GET_INST(JPEG, inst_idx), \
80 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
82 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
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H A Dvcn_v3_0.c573 int inst_idx = vinst->inst; in vcn_v3_0_mc_resume_dpg_mode() local
910 int inst_idx = vinst->inst; in vcn_v3_0_clock_gating_dpg_mode() local
1028 int inst_idx = vinst->inst; in vcn_v3_0_start_dpg_mode() local
1043 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v3_0_start_dpg_mode()
1072 VCN, inst_idx, mmUVD_MPC_CNTL), in vcn_v3_0_start_dpg_mode()
1076 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), in vcn_v3_0_start_dpg_mode()
1083 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), in vcn_v3_0_start_dpg_mode()
1090 VCN, inst_idx, mmUVD_MPC_SET_MUX), in vcn_v3_0_start_dpg_mode()
1117 VCN, inst_idx, mmUVD_MASTINT_EN), in vcn_v3_0_start_dpg_mode()
1578 int inst_idx = vinst->inst; in vcn_v3_0_stop_dpg_mode() local
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H A Dvcn_v4_0.c524 int inst_idx = vinst->inst; in vcn_v4_0_mc_resume_dpg_mode() local
870 int inst_idx = vinst->inst; in vcn_v4_0_disable_clock_gating_dpg_mode() local
979 int inst_idx = vinst->inst; in vcn_v4_0_enable_ras() local
989 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_enable_ras()
994 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_enable_ras()
1010 int inst_idx = vinst->inst; in vcn_v4_0_start_dpg_mode() local
1025 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v4_0_start_dpg_mode()
1053 VCN, inst_idx, regUVD_MPC_CNTL), in vcn_v4_0_start_dpg_mode()
1092 VCN, inst_idx, regUVD_MASTINT_EN), in vcn_v4_0_start_dpg_mode()
1567 int inst_idx = vinst->inst; in vcn_v4_0_stop_dpg_mode() local
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H A Damdgpu_vcn.h82 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
87 RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
94 WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
101 #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) \ argument
136 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
140 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \
162 #define SOC24_DPG_MODE_OFFSET(ip, inst_idx, reg) \ argument
198 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \
201 VCN, GET_INST(VCN, inst_idx), \
207 *adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ = \
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H A Dvcn_v5_0_1.c381 int inst_idx = vinst->inst; in vcn_v5_0_1_mc_resume_dpg_mode() local
394 inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
398 inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
563 int inst_idx = vinst->inst; in vcn_v5_0_1_start_dpg_mode() local
565 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; in vcn_v5_0_1_start_dpg_mode()
571 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v5_0_1_start_dpg_mode()
586 WREG32_SOC24_DPG_MODE(inst_idx, 0xDEADBEEF, in vcn_v5_0_1_start_dpg_mode()
587 adev->vcn.inst[inst_idx].aid_id, 0, true); in vcn_v5_0_1_start_dpg_mode()
635 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; in vcn_v5_0_1_start_dpg_mode()
825 int inst_idx = vinst->inst; in vcn_v5_0_1_stop_dpg_mode() local
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H A Dvcn_v2_5.c667 int inst_idx = vinst->inst; in vcn_v2_5_mc_resume_dpg_mode() local
882 int inst_idx = vinst->inst; in vcn_v2_5_clock_gating_dpg_mode() local
993 int inst_idx = vinst->inst; in vcn_v2_6_enable_ras() local
1003 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
1008 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
1013 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v2_6_enable_ras()
1021 int inst_idx = vinst->inst; in vcn_v2_5_start_dpg_mode() local
1036 …adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_ad… in vcn_v2_5_start_dpg_mode()
1118 ring = &adev->vcn.inst[inst_idx].ring_dec; in vcn_v2_5_start_dpg_mode()
1548 int inst_idx = vinst->inst; in vcn_v2_5_stop_dpg_mode() local
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H A Dvcn_v4_0_3.c99 int inst_idx, bool indirect);
444 int inst_idx = vinst->inst; in vcn_v4_0_3_mc_resume() local
521 int inst_idx = vinst->inst; in vcn_v4_0_3_mc_resume_dpg_mode() local
635 int inst_idx = vinst->inst; in vcn_v4_0_3_disable_clock_gating() local
733 int inst_idx = vinst->inst; in vcn_v4_0_3_disable_clock_gating_dpg_mode() local
782 int inst_idx = vinst->inst; in vcn_v4_0_3_enable_clock_gating() local
836 int inst_idx = vinst->inst; in vcn_v4_0_3_start_dpg_mode() local
855 inst_idx, adev->vcn.inst[inst_idx].aid_id); in vcn_v4_0_3_start_dpg_mode()
1339 int inst_idx = vinst->inst; in vcn_v4_0_3_stop_dpg_mode() local
2060 WREG32_SOC15_DPG_MODE(inst_idx, in vcn_v4_0_3_enable_ras()
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H A Djpeg_v5_0_0.c304 int inst_idx, uint8_t indirect) in jpeg_engine_5_0_0_dpg_clock_gating_mode() argument
343 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; in jpeg_v5_0_0_start_dpg_mode()
354 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr = in jpeg_v5_0_0_start_dpg_mode()
355 (uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr; in jpeg_v5_0_0_start_dpg_mode()
369 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_SYS_INT_EN, in jpeg_v5_0_0_start_dpg_mode()
372 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_SYS_INT_EN, in jpeg_v5_0_0_start_dpg_mode()
379 amdgpu_jpeg_psp_update_sram(adev, inst_idx, 0); in jpeg_v5_0_0_start_dpg_mode()
386 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v5_0_0_start_dpg_mode()
388 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v5_0_0_start_dpg_mode()
392 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_RPTR, 0); in jpeg_v5_0_0_start_dpg_mode()
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H A Djpeg_v4_0_5.c355 int inst_idx, uint8_t indirect) in jpeg_engine_4_0_5_dpg_clock_gating_mode() argument
422 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec; in jpeg_v4_0_5_start_dpg_mode()
434 SOC15_WAIT_ON_RREG(JPEG, inst_idx, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_start_dpg_mode()
444 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr = in jpeg_v4_0_5_start_dpg_mode()
445 (uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr; in jpeg_v4_0_5_start_dpg_mode()
460 amdgpu_jpeg_psp_update_sram(adev, inst_idx, 0); in jpeg_v4_0_5_start_dpg_mode()
462 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_VMID, 0); in jpeg_v4_0_5_start_dpg_mode()
464 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW, in jpeg_v4_0_5_start_dpg_mode()
466 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, in jpeg_v4_0_5_start_dpg_mode()
468 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_RPTR, 0); in jpeg_v4_0_5_start_dpg_mode()
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H A Damdgpu_jpeg.c337 int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx, in amdgpu_jpeg_psp_update_sram() argument
342 .mc_addr = adev->jpeg.inst[inst_idx].dpg_sram_gpu_addr, in amdgpu_jpeg_psp_update_sram()
343 .ucode_size = ((uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_curr_addr - in amdgpu_jpeg_psp_update_sram()
344 (uintptr_t)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr), in amdgpu_jpeg_psp_update_sram()
H A Dvcn_v1_0.c1273 int inst_idx = vinst->inst; in vcn_v1_0_pause_dpg_mode() local
1280 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v1_0_pause_dpg_mode()
1282 adev->vcn.inst[inst_idx].pause_state.fw_based, in vcn_v1_0_pause_dpg_mode()
1283 adev->vcn.inst[inst_idx].pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1332 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v1_0_pause_dpg_mode()
1336 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { in vcn_v1_0_pause_dpg_mode()
1338 adev->vcn.inst[inst_idx].pause_state.fw_based, in vcn_v1_0_pause_dpg_mode()
1339 adev->vcn.inst[inst_idx].pause_state.jpeg, in vcn_v1_0_pause_dpg_mode()
1393 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; in vcn_v1_0_pause_dpg_mode()
H A Damdgpu_vcn.c1312 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, in amdgpu_vcn_psp_update_sram() argument
1317 (inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM : in amdgpu_vcn_psp_update_sram()
1319 .mc_addr = adev->vcn.inst[inst_idx].dpg_sram_gpu_addr, in amdgpu_vcn_psp_update_sram()
1320 .ucode_size = ((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr - in amdgpu_vcn_psp_update_sram()
1321 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr), in amdgpu_vcn_psp_update_sram()
H A Djpeg_v4_0_3.c480 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) in jpeg_v4_0_3_disable_clock_gating() argument
485 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_disable_clock_gating()
505 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) in jpeg_v4_0_3_enable_clock_gating() argument
510 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_enable_clock_gating()
H A Dvcn_v2_0.c1262 int inst_idx = vinst->inst; in vcn_v2_0_pause_dpg_mode() local
1268 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) { in vcn_v2_0_pause_dpg_mode()
1270 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based); in vcn_v2_0_pause_dpg_mode()
1331 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based; in vcn_v2_0_pause_dpg_mode()
H A Daqua_vanjaram.c71 uint32_t inst_idx, struct amdgpu_ring *ring) in aqua_vanjaram_set_xcp_id() argument
84 inst_mask = 1 << inst_idx; in aqua_vanjaram_set_xcp_id()