80 #define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) 			\  argument
81 	({	WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); 			\
82 		WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, 				\
84 			((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) 	\
87 		RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); 			\
90 #define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) 		\  argument
92 		WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); 			\
93 		WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); 			\
94 		WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, 				\
96 			((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) 	\
101 #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) 						\  argument
106 		addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg);		\
134 #define RREG32_SOC15_DPG_MODE(inst_idx, offset, mask_en) 					\  argument
136 		WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, 					\
140 		RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA);				\
143 #define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect)             \  argument
146 			WREG32_SOC15(VCN, GET_INST(VCN, inst_idx),                    \
149 				VCN, GET_INST(VCN, inst_idx),                         \
155 			*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ =              \
157 			*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ =              \
162 #define SOC24_DPG_MODE_OFFSET(ip, inst_idx, reg)						\  argument
167 		addr = (adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg);		\
195 #define WREG32_SOC24_DPG_MODE(inst_idx, offset, value, mask_en, indirect)		\  argument
198 			WREG32_SOC15(VCN, GET_INST(VCN, inst_idx),			\
201 				VCN, GET_INST(VCN, inst_idx),				\
207 			*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ =		\
209 			*adev->vcn.inst[inst_idx].dpg_sram_curr_addr++ =		\
546 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx,