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Searched refs:i915 (Results 1 – 25 of 449) sorted by relevance

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/linux-6.15/drivers/gpu/drm/i915/
H A Di915_drv.h391 #define INTEL_INFO(i915) ((i915)->__info) argument
393 #define DRIVER_CAPS(i915) (&(i915)->caps) argument
501 #define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915)) argument
536 #define IS_LUNARLAKE(i915) (0 && i915) argument
537 #define IS_BATTLEMAGE(i915) (0 && i915) argument
538 #define IS_PANTHERLAKE(i915) (0 && i915) argument
596 #define IS_GEN9_LP(i915) (IS_BROXTON(i915) || IS_GEMINILAKE(i915)) argument
597 #define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_GEN9_LP(i915)) argument
634 #define HAS_WT(i915) HAS_EDRAM(i915) argument
684 #define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915)) argument
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H A Dintel_clock_gating.c48 if (HAS_LLC(i915)) { in gen9_init_clock_gating()
356 if (!HAS_PCH_CNP(i915)) in cnp_init_clock_gating()
386 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) in kbl_init_clock_gating()
391 if (IS_KABYLAKE(i915) && IS_GRAPHICS_STEP(i915, 0, STEP_C0)) in kbl_init_clock_gating()
610 if (IS_GM45(i915)) in g4x_init_clock_gating()
612 intel_uncore_write(&i915->uncore, DSPCLK_GATE_D(i915), dspclk_gate); in g4x_init_clock_gating()
651 if (IS_PINEVIEW(i915)) in gen3_init_clock_gating()
701 i915->clock_gating_funcs->init_clock_gating(i915); in intel_clock_gating_init()
748 if (IS_DG2(i915)) in intel_clock_gating_hooks_init()
750 else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) in intel_clock_gating_hooks_init()
[all …]
H A Dvlv_sideband.h36 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT)); in vlv_bunit_get()
44 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT)); in vlv_bunit_put()
49 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK)); in vlv_cck_get()
57 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK)); in vlv_cck_put()
62 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU)); in vlv_ccu_get()
70 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU)); in vlv_ccu_put()
75 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO)); in vlv_dpio_get()
84 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO)); in vlv_dpio_put()
102 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_NC)); in vlv_nc_get()
109 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_NC)); in vlv_nc_put()
[all …]
H A Dvlv_sideband.c45 if (IS_VALLEYVIEW(i915)) { in __vlv_punit_get()
53 if (IS_VALLEYVIEW(i915)) in __vlv_punit_put()
63 __vlv_punit_get(i915); in vlv_iosf_sb_get()
65 mutex_lock(&i915->vlv_iosf_sb.lock); in vlv_iosf_sb_get()
70 mutex_unlock(&i915->vlv_iosf_sb.lock); in vlv_iosf_sb_put()
73 __vlv_punit_put(i915); in vlv_iosf_sb_put()
206 if (IS_CHERRYVIEW(i915)) in vlv_dpio_phy_iosf_port()
255 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in vlv_iosf_sb_init()
258 if (IS_VALLEYVIEW(i915)) in vlv_iosf_sb_init()
264 if (IS_VALLEYVIEW(i915)) in vlv_iosf_sb_fini()
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H A Di915_getparam.c39 value = to_gt(i915)->ggtt->num_fences; in i915_getparam_ioctl()
45 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
49 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
53 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
61 value = HAS_LLC(i915); in i915_getparam_ioctl()
64 value = HAS_WT(i915); in i915_getparam_ioctl()
67 value = INTEL_PPGTT(i915); in i915_getparam_ioctl()
90 intel_has_gpu_reset(to_gt(i915)); in i915_getparam_ioctl()
98 value = HAS_POOLED_EU(i915); in i915_getparam_ioctl()
105 if (i915->media_gt) in i915_getparam_ioctl()
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H A Di915_driver.c416 if (IS_I965G(i915) || IS_I965GM(i915)) in i915_set_dma_info()
433 if (IS_DG2(i915)) { in i915_enable_g8()
455 i915_enable_g8(i915); in i915_pcode_init()
746 if (IS_ERR(i915)) in i915_driver_create()
747 return i915; in i915_driver_create()
759 return i915; in i915_driver_create()
786 if (IS_ERR(i915)) { in i915_driver_probe()
788 return PTR_ERR(i915); in i915_driver_probe()
986 if (HAS_DISPLAY(i915)) in i915_driver_shutdown()
1341 if (!i915) { in i915_pm_prepare()
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H A Di915_switcheroo.c15 struct drm_i915_private *i915 = pdev_to_i915(pdev); in i915_switcheroo_set_state() local
18 if (!i915) { in i915_switcheroo_set_state()
22 if (!HAS_DISPLAY(i915)) { in i915_switcheroo_set_state()
28 drm_info(&i915->drm, "switched on\n"); in i915_switcheroo_set_state()
32 i915_driver_resume_switcheroo(i915); in i915_switcheroo_set_state()
35 drm_info(&i915->drm, "switched off\n"); in i915_switcheroo_set_state()
37 i915_driver_suspend_switcheroo(i915, pmm); in i915_switcheroo_set_state()
44 struct drm_i915_private *i915 = pdev_to_i915(pdev); in i915_switcheroo_can_switch() local
51 return i915 && HAS_DISPLAY(i915) && atomic_read(&i915->drm.open_count) == 0; in i915_switcheroo_can_switch()
62 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); in i915_switcheroo_register()
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H A Dintel_step.c152 int revid = INTEL_REVID(i915); in intel_step_init()
155 if (HAS_GMD_ID(i915)) { in intel_step_init()
166 if (IS_DG2_G10(i915)) { in intel_step_init()
169 } else if (IS_DG2_G11(i915)) { in intel_step_init()
172 } else if (IS_DG2_G12(i915)) { in intel_step_init()
190 } else if (IS_DG1(i915)) { in intel_step_init()
202 } else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) { in intel_step_init()
205 } else if (IS_ICELAKE(i915)) { in intel_step_init()
211 } else if (IS_BROXTON(i915)) { in intel_step_init()
214 } else if (IS_KABYLAKE(i915)) { in intel_step_init()
[all …]
/linux-6.15/drivers/gpu/drm/i915/soc/
H A Dintel_gmch.c51 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp_lo); in intel_alloc_mchbar_resource()
75 pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915) + 4, in intel_alloc_mchbar_resource()
78 pci_write_config_dword(i915->gmch.pdev, mchbar_reg(i915), in intel_alloc_mchbar_resource()
89 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) in intel_gmch_bar_setup()
94 if (IS_I915G(i915) || IS_I915GM(i915)) { in intel_gmch_bar_setup()
98 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp); in intel_gmch_bar_setup()
112 if (IS_I915G(i915) || IS_I915GM(i915)) { in intel_gmch_bar_setup()
116 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), &temp); in intel_gmch_bar_setup()
124 if (IS_I915G(i915) || IS_I915GM(i915)) { in intel_gmch_bar_teardown()
135 pci_read_config_dword(i915->gmch.pdev, mchbar_reg(i915), in intel_gmch_bar_teardown()
[all …]
H A Dintel_dram.c130 i915->mem_freq = pnv_mem_freq(i915); in detect_mem_freq()
132 i915->mem_freq = ilk_mem_freq(i915); in detect_mem_freq()
134 i915->mem_freq = chv_mem_freq(i915); in detect_mem_freq()
136 i915->mem_freq = vlv_mem_freq(i915); in detect_mem_freq()
139 i915->is_ddr3 = pnv_is_ddr3(i915); in detect_mem_freq()
159 if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) { in i9xx_fsb_freq()
230 i915->fsb_freq = ilk_fsb_freq(i915); in detect_fsb_freq()
232 i915->fsb_freq = i9xx_fsb_freq(i915); in detect_fsb_freq()
687 drm_WARN_ON(&i915->drm, !IS_DGFX(i915)); in xelpdp_get_dram_info()
714 if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915)) in intel_dram_detect()
[all …]
/linux-6.15/drivers/gpu/drm/i915/selftests/
H A Dmock_gem_device.c63 if (!i915->do_release) in mock_device_release()
66 mock_device_flush(i915); in mock_device_release()
167 if (IS_ERR(i915)) { in mock_gem_device()
202 i915_gem_init__mm(i915); in mock_gem_device()
204 mock_uncore_init(&i915->uncore, i915); in mock_gem_device()
207 mock_gt_probe(i915); in mock_gem_device()
214 if (!i915->wq) in mock_gem_device()
218 if (!i915->unordered_wq) in mock_gem_device()
229 to_gt(i915)->vm = i915_vm_get(&to_gt(i915)->ggtt->vm); in mock_gem_device()
233 to_gt(i915)->engine[RCS0] = mock_engine(i915, "mock", RCS0); in mock_gem_device()
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H A Di915_gem.c90 trash_stolen(i915); in simulate_hibernate()
97 i915_gem_suspend(i915); in igt_pm_prepare()
119 i915_gem_freeze(i915); in igt_pm_hibernate()
136 i915_gem_resume(i915); in igt_pm_resume()
147 file = mock_file(i915); in igt_gem_suspend()
162 igt_pm_suspend(i915); in igt_gem_suspend()
165 simulate_hibernate(i915); in igt_gem_suspend()
167 igt_pm_resume(i915); in igt_gem_suspend()
182 file = mock_file(i915); in igt_gem_hibernate()
197 igt_pm_hibernate(i915); in igt_gem_hibernate()
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/linux-6.15/drivers/gpu/drm/i915/gem/
H A Di915_gem_stolen.c101 !IS_G33(i915) && !IS_PINEVIEW(i915) && !IS_G4X(i915)) { in adjust_stolen()
154 if (HAS_LMEM(i915) || HAS_LMEMBAR_SMEM_STOLEN(i915)) in request_smem_stolen()
224 drm_WARN(&i915->drm, GRAPHICS_VER(i915) == 5, in g4x_get_stolen_reserved()
460 if (IS_CHERRYVIEW(i915) || IS_BROXTON(i915) || IS_GEMINILAKE(i915)) in init_reserved_stolen()
476 } else if (GRAPHICS_VER(i915) >= 5 || IS_G4X(i915)) { in init_reserved_stolen()
498 &i915->dsm.reserved, &i915->dsm.stolen); in init_reserved_stolen()
513 struct drm_i915_private *i915 = mem->i915; in i915_gem_init_stolen() local
524 if (i915_vtd_active(i915) && GRAPHICS_VER(i915) < 8) { in i915_gem_init_stolen()
566 if (IS_METEORLAKE(i915) && INTEL_REVID(i915) == 0x0) in i915_gem_init_stolen()
743 struct drm_i915_private *i915 = mem->i915; in _i915_gem_object_stolen_init() local
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H A Di915_gem_pm.c38 flush_workqueue(i915->wq); in i915_gem_suspend()
49 for_each_gt(gt, i915, i) in i915_gem_suspend()
106 i915_gem_suspend(i915); in i915_gem_backup_suspend()
132 lmem_recover(i915); in i915_gem_backup_suspend()
141 &i915->mm.shrink_list, in i915_gem_suspend_late()
142 &i915->mm.purge_list, in i915_gem_suspend_late()
173 for_each_gt(gt, i915, i) in i915_gem_suspend_late()
194 i915_gem_shrink_all(i915); in i915_gem_freeze()
245 for_each_gt(gt, i915, i) in i915_gem_resume()
255 for_each_gt(gt, i915, j) { in i915_gem_resume()
[all …]
H A Di915_gem_shrinker.c115 &i915->mm.shrink_list, in i915_gem_shrink()
153 for_each_gt(gt, i915, i) in i915_gem_shrink()
404 for_each_gt(gt, i915, i) { in i915_gem_shrinker_vmap()
432 if (!i915->mm.shrinker) { in i915_gem_driver_register__shrinker()
438 i915->mm.shrinker->private_data = i915; in i915_gem_driver_register__shrinker()
444 drm_WARN_ON(&i915->drm, register_oom_notifier(&i915->mm.oom_notifier)); in i915_gem_driver_register__shrinker()
447 drm_WARN_ON(&i915->drm, in i915_gem_driver_register__shrinker()
453 drm_WARN_ON(&i915->drm, in i915_gem_driver_unregister__shrinker()
455 drm_WARN_ON(&i915->drm, in i915_gem_driver_unregister__shrinker()
502 i915->mm.shrink_count--; in i915_gem_object_make_unshrinkable()
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/linux-6.15/drivers/gpu/drm/xe/
H A DMakefile170 $(obj)/i915-soc/%.o: $(srctree)/drivers/gpu/drm/i915/soc/%.c FORCE
175 $(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
198 i915-soc/intel_dram.o \
199 i915-soc/intel_pch.o \
200 i915-soc/intel_rom.o
204 i915-display/icl_dsi.o \
211 i915-display/intel_bw.o \
237 i915-display/intel_dp.o \
253 i915-display/intel_fb.o \
280 i915-display/intel_tc.o \
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/linux-6.15/drivers/gpu/drm/xe/compat-i915-headers/
H A Dvlv_sideband.h34 static inline void vlv_iosf_sb_write(struct drm_i915_private *i915, in vlv_iosf_sb_write() argument
41 static inline void vlv_bunit_get(struct drm_i915_private *i915) in vlv_bunit_get() argument
51 static inline void vlv_bunit_put(struct drm_i915_private *i915) in vlv_bunit_put() argument
54 static inline void vlv_cck_get(struct drm_i915_private *i915) in vlv_cck_get() argument
64 static inline void vlv_cck_put(struct drm_i915_private *i915) in vlv_cck_put() argument
67 static inline void vlv_ccu_get(struct drm_i915_private *i915) in vlv_ccu_get() argument
77 static inline void vlv_ccu_put(struct drm_i915_private *i915) in vlv_ccu_put() argument
80 static inline void vlv_dpio_get(struct drm_i915_private *i915) in vlv_dpio_get() argument
91 static inline void vlv_dpio_put(struct drm_i915_private *i915) in vlv_dpio_put() argument
107 static inline void vlv_nc_get(struct drm_i915_private *i915) in vlv_nc_get() argument
[all …]
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_display_irq.h18 void valleyview_enable_display_irqs(struct drm_i915_private *i915);
21 void ilk_update_display_irq(struct drm_i915_private *i915,
30 void ibx_display_interrupt_update(struct drm_i915_private *i915,
57 void i9xx_display_irq_reset(struct drm_i915_private *i915);
58 void vlv_display_irq_reset(struct drm_i915_private *i915);
59 void gen8_display_irq_reset(struct drm_i915_private *i915);
60 void gen11_display_irq_reset(struct drm_i915_private *i915);
63 void ilk_de_irq_postinstall(struct drm_i915_private *i915);
64 void gen8_de_irq_postinstall(struct drm_i915_private *i915);
66 void dg1_de_irq_postinstall(struct drm_i915_private *i915);
[all …]
H A Dintel_modeset_setup.c61 drm_dbg_kms(&i915->drm, in intel_crtc_disable_noatomic_begin()
87 drm_dbg_kms(&i915->drm, in intel_crtc_disable_noatomic_begin()
275 drm_WARN_ON(&i915->drm, in intel_crtc_disable_noatomic()
390 drm_dbg_kms(&i915->drm, in intel_sanitize_plane_mapping()
595 drm_dbg_kms(&i915->drm, in intel_sanitize_encoder()
603 drm_dbg_kms(&i915->drm, in intel_sanitize_encoder()
654 if (HAS_DDI(i915)) in intel_sanitize_encoder()
679 drm_dbg_kms(&i915->drm, in readout_plane_state()
719 drm_dbg_kms(&i915->drm, in intel_modeset_readout_hw_state()
921 if (IS_HASWELL(i915)) in intel_early_display_was()
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H A Dintel_display_wa.c11 static void gen11_display_wa_apply(struct drm_i915_private *i915) in gen11_display_wa_apply() argument
14 intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP); in gen11_display_wa_apply()
17 static void xe_d_display_wa_apply(struct drm_i915_private *i915) in xe_d_display_wa_apply() argument
26 intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS); in adlp_display_wa_apply()
32 void intel_display_wa_apply(struct drm_i915_private *i915) in intel_display_wa_apply() argument
34 if (IS_ALDERLAKE_P(i915)) in intel_display_wa_apply()
35 adlp_display_wa_apply(i915); in intel_display_wa_apply()
36 else if (DISPLAY_VER(i915) == 12) in intel_display_wa_apply()
37 xe_d_display_wa_apply(i915); in intel_display_wa_apply()
38 else if (DISPLAY_VER(i915) == 11) in intel_display_wa_apply()
[all …]
H A Dintel_hotplug_irq.c542 drm_dbg(&i915->drm, in xelpdp_pica_irq_handler()
553 drm_err(&i915->drm, in xelpdp_pica_irq_handler()
899 dg1_hpd_invert(i915); in dg1_hpd_enable_detection()
1054 mtp_hpd_invert(i915); in mtp_hpd_enable_detection()
1142 enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.hpd); in xelpdp_hpd_irq_setup()
1143 hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.hpd); in xelpdp_hpd_irq_setup()
1390 if (IS_G45(i915)) in i915_hpd_enable_detection()
1440 HPD_FUNCS(i915);
1460 if ((IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) && in intel_hpd_irq_setup()
1465 i915->display.funcs.hotplug->hpd_irq_setup(i915); in intel_hpd_irq_setup()
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/linux-6.15/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp.c166 return to_gt(i915); in find_gt_for_required_teelink()
173 if (!HAS_PXP(i915)) in find_gt_for_required_protected_content()
182 if (i915->media_gt && HAS_ENGINE(i915->media_gt, GSC0) && in find_gt_for_required_protected_content()
192 return to_gt(i915); in find_gt_for_required_protected_content()
223 i915->pxp = kzalloc(sizeof(*i915->pxp), GFP_KERNEL); in intel_pxp_init()
224 if (!i915->pxp) in intel_pxp_init()
246 if (!i915->pxp) in intel_pxp_fini()
258 kfree(i915->pxp); in intel_pxp_fini()
259 i915->pxp = NULL; in intel_pxp_fini()
353 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; in intel_pxp_end() local
[all …]
H A Dintel_pxp_tee.c63 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; in intel_pxp_tee_io_message() local
93 drm_err(&i915->drm, in intel_pxp_tee_io_message()
115 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; in intel_pxp_tee_stream_message() local
169 if (!HAS_HECI_PXP(i915)) { in i915_pxp_tee_component_bind()
231 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; in alloc_streaming_command() local
239 if (!IS_DGFX(i915)) in alloc_streaming_command()
295 struct drm_i915_private *i915 = gt->i915; in intel_pxp_tee_component_init() local
319 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; in intel_pxp_tee_component_fini() local
333 struct drm_i915_private *i915 = pxp->ctrl_gt->i915; in intel_pxp_tee_cmd_create_arb_session() local
353 drm_info_once(&i915->drm, in intel_pxp_tee_cmd_create_arb_session()
[all …]
/linux-6.15/drivers/gpu/drm/ci/xfails/
H A Di915-glk-skips.txt34 # i915 0000:00:02.0: [drm] drm_WARN_ON(intel_dp->pps.vdd_wakeref)
78 # i915 0000:00:02.0: [drm] *ERROR* PPS state mismatch
111 # i915 0000:00:02.0: [drm] *ERROR* Failed to read DPCD register 0x92
145 # i915 0000:00:02.0: [drm] *ERROR* [CRTC:70:pipe A] flip_done timed out
146 # i915 0000:00:02.0: [drm] *ERROR* flip_done timed out
147 # i915 0000:00:02.0: [drm] *ERROR* [CRTC:70:pipe A] commit wait timed out
181 # i915 0000:00:02.0: [drm] drm_WARN_ON(intel_dp->pps.vdd_wakeref)
225 # i915 0000:00:02.0: [drm] *ERROR* PPS state mismatch
258 # i915 0000:00:02.0: [drm] *ERROR* Failed to read DPCD register 0x92
293 # i915 0000:00:02.0: [drm] *ERROR* [CRTC:70:pipe A] flip_done timed out
[all …]
/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dintel_wopcm.c81 struct drm_i915_private *i915 = gt->i915; in intel_wopcm_init_early() local
83 if (!HAS_GT_UC(i915)) in intel_wopcm_init_early()
86 if (GRAPHICS_VER(i915) >= 11) in intel_wopcm_init_early()
96 if (IS_GEN9_LP(i915)) in context_reserved_size()
117 drm_err(&i915->drm, in gen9_check_dword_gap()
150 if (GRAPHICS_VER(i915) == 9 && !gen9_check_dword_gap(i915, guc_wopcm_base, in check_hw_restrictions()
154 if (GRAPHICS_VER(i915) == 9 && in check_hw_restrictions()
165 struct drm_i915_private *i915 = gt->i915; in __check_layout() local
171 drm_err(&i915->drm, in __check_layout()
236 struct drm_i915_private *i915 = gt->i915; in intel_wopcm_init() local
[all …]

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