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Searched refs:field_val (Results 1 – 11 of 11) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvega20_ih.c676 uint32_t data, def, field_val; in vega20_ih_update_clockgating_state() local
680 field_val = enable ? 0 : 1; in vega20_ih_update_clockgating_state()
682 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val); in vega20_ih_update_clockgating_state()
684 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); in vega20_ih_update_clockgating_state()
686 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); in vega20_ih_update_clockgating_state()
688 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); in vega20_ih_update_clockgating_state()
690 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); in vega20_ih_update_clockgating_state()
692 DYN_CLK_SOFT_OVERRIDE, field_val); in vega20_ih_update_clockgating_state()
694 REG_CLK_SOFT_OVERRIDE, field_val); in vega20_ih_update_clockgating_state()
H A Dvega10_ih.c580 uint32_t data, def, field_val; in vega10_ih_update_clockgating_state() local
584 field_val = enable ? 0 : 1; in vega10_ih_update_clockgating_state()
590 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
593 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
595 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
597 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
599 DYN_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
601 REG_CLK_SOFT_OVERRIDE, field_val); in vega10_ih_update_clockgating_state()
H A Dnavi10_ih.c649 uint32_t data, def, field_val; in navi10_ih_update_clockgating_state() local
653 field_val = enable ? 0 : 1; in navi10_ih_update_clockgating_state()
655 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); in navi10_ih_update_clockgating_state()
657 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); in navi10_ih_update_clockgating_state()
659 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); in navi10_ih_update_clockgating_state()
661 DYN_CLK_SOFT_OVERRIDE, field_val); in navi10_ih_update_clockgating_state()
663 REG_CLK_SOFT_OVERRIDE, field_val); in navi10_ih_update_clockgating_state()
H A Dih_v6_0.c676 uint32_t data, def, field_val; in ih_v6_0_update_clockgating_state() local
680 field_val = enable ? 0 : 1; in ih_v6_0_update_clockgating_state()
682 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); in ih_v6_0_update_clockgating_state()
684 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); in ih_v6_0_update_clockgating_state()
686 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); in ih_v6_0_update_clockgating_state()
688 DYN_CLK_SOFT_OVERRIDE, field_val); in ih_v6_0_update_clockgating_state()
690 REG_CLK_SOFT_OVERRIDE, field_val); in ih_v6_0_update_clockgating_state()
H A Dih_v6_1.c655 uint32_t data, def, field_val; in ih_v6_1_update_clockgating_state() local
659 field_val = enable ? 0 : 1; in ih_v6_1_update_clockgating_state()
661 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); in ih_v6_1_update_clockgating_state()
663 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); in ih_v6_1_update_clockgating_state()
665 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); in ih_v6_1_update_clockgating_state()
667 DYN_CLK_SOFT_OVERRIDE, field_val); in ih_v6_1_update_clockgating_state()
669 REG_CLK_SOFT_OVERRIDE, field_val); in ih_v6_1_update_clockgating_state()
H A Dih_v7_0.c645 uint32_t data, def, field_val; in ih_v7_0_update_clockgating_state() local
649 field_val = enable ? 0 : 1; in ih_v7_0_update_clockgating_state()
651 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val); in ih_v7_0_update_clockgating_state()
653 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val); in ih_v7_0_update_clockgating_state()
655 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val); in ih_v7_0_update_clockgating_state()
657 DYN_CLK_SOFT_OVERRIDE, field_val); in ih_v7_0_update_clockgating_state()
659 REG_CLK_SOFT_OVERRIDE, field_val); in ih_v7_0_update_clockgating_state()
H A Damdgpu_psp.h490 uint32_t field_val, uint32_t mask, bool check_changed);
492 uint32_t field_val, uint32_t mask, uint32_t msec_timeout);
H A Damdgpu.h1386 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ argument
1388 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
/linux-6.15/drivers/gpu/drm/amd/include/
H A Dcgs_common.h123 #define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \ argument
125 (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field))))
/linux-6.15/drivers/net/pse-pd/
H A Dtps23881.c102 u16 field_mask, u16 field_val) in tps23881_set_val() argument
104 field_val &= field_mask; in tps23881_set_val()
108 reg_val |= (field_val << field_offset); in tps23881_set_val()
111 reg_val |= (field_val << (field_offset + 8)); in tps23881_set_val()
/linux-6.15/drivers/phy/cadence/
H A Dphy-cadence-torrent.c1276 u32 read_val, field_val; in cdns_torrent_dp_configure_rate() local
1283 ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val); in cdns_torrent_dp_configure_rate()
1286 field_val &= ~(cdns_phy->dp_pll); in cdns_torrent_dp_configure_rate()
1287 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val); in cdns_torrent_dp_configure_rate()
1327 ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val); in cdns_torrent_dp_configure_rate()
1330 field_val |= cdns_phy->dp_pll; in cdns_torrent_dp_configure_rate()
1331 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val); in cdns_torrent_dp_configure_rate()