| /linux-6.15/drivers/gpu/drm/i915/display/ |
| H A D | intel_display_driver.c | 88 if (!HAS_DISPLAY(display)) in intel_display_driver_init_hw()
94 intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK"); in intel_display_driver_init_hw()
151 if (display->platform.i845g || display->platform.i865g) { in intel_mode_config_init()
154 } else if (display->platform.i830 || display->platform.i85x || in intel_mode_config_init()
155 display->platform.i915g || display->platform.i915gm) { in intel_mode_config_init()
241 intel_dmc_init(display); in intel_display_driver_probe_noirq()
272 intel_fbc_init(display); in intel_display_driver_probe_noirq()
277 intel_dmc_fini(display); in intel_display_driver_probe_noirq()
485 if (!HAS_GMCH(display)) in intel_display_driver_probe_nogem()
724 if (!HAS_GMCH(display)) in __intel_display_driver_resume()
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| H A D | i9xx_display_sr.c | 22 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
23 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
26 display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); in i9xx_display_save_swf()
29 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
32 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
33 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
36 display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); in i9xx_display_save_swf()
47 intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]); in i9xx_display_restore_swf()
48 intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]); in i9xx_display_restore_swf()
51 intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]); in i9xx_display_restore_swf()
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| H A D | intel_display_power.c | 940 else if (display->platform.geminilake || display->platform.broxton) in get_allowed_dc_mask()
952 mask = display->platform.geminilake || display->platform.broxton || in get_allowed_dc_mask()
1007 get_allowed_dc_mask(display, display->params.enable_dc); in intel_power_domains_init()
1131 if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14) in icl_mbus_init()
1197 intel_de_read(display, PP_STATUS(display, 0)) & PP_ON, in assert_can_disable_lcpll()
1597 if (display->platform.dgfx && !display->platform.dg1) in tgl_bw_buddy_init()
1672 if (DISPLAY_VER(display) == 12 || display->platform.dg2) in icl_display_core_init()
1781 u32 status = intel_de_read(display, DPLL(display, PIPE_A)); in chv_phy_control_init()
2115 else if (display->platform.geminilake || display->platform.broxton) in intel_power_domains_suspend()
2245 if (DISPLAY_VER(display) >= 11 || display->platform.geminilake || in intel_display_power_suspend_late()
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| H A D | intel_display_power_well.c | 416 drm_WARN_ON(display->drm, !display->platform.icelake); in icl_combo_phy_aux_power_well_enable()
443 drm_WARN_ON(display->drm, !display->platform.icelake); in icl_combo_phy_aux_power_well_disable()
601 if (DISPLAY_VER(display) == 9 && !display->platform.broxton && in hsw_power_well_enabled()
831 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) in gen9_enable_dc5()
862 if (DISPLAY_VER(display) == 9 && !display->platform.broxton) in skl_enable_dc6()
880 if (display->platform.broxton || display->platform.geminilake) in bxt_enable_dc9()
1186 intel_de_rmw(display, DSPCLK_GATE_D(display), in vlv_init_display_clock_gating()
1217 u32 val = intel_de_read(display, DPLL(display, pipe)); in vlv_display_power_well_init()
1223 intel_de_write(display, DPLL(display, pipe), val); in vlv_display_power_well_init()
1837 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), in xelpdp_aux_power_well_enable()
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| H A D | intel_fdi.c | 32 if (HAS_DDI(display)) { in assert_fdi_tx()
90 if (HAS_DDI(display)) in assert_fdi_tx_pll_enabled()
145 if (!display->platform.ivybridge || INTEL_NUM_PIPES(display) != 3) in intel_fdi_add_affected_crtcs()
193 drm_dbg_kms(display->drm, in ilk_check_fdi_lanes()
203 if (display->platform.haswell || display->platform.broadwell) { in ilk_check_fdi_lanes()
275 } else if (display->platform.sandybridge || display->platform.ivybridge) { in intel_fdi_pll_freq_update()
281 drm_dbg(display->drm, "FDI PLL freq=%d\n", display->fdi.pll_freq); in intel_fdi_pll_freq_update()
287 if (HAS_DDI(display)) in intel_fdi_link_freq()
518 intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK); in ilk_fdi_link_train()
620 intel_de_read(display, PIPE_DATA_M1(display, pipe)) & TU_SIZE_MASK); in gen6_fdi_link_train()
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| H A D | intel_cdclk.c | 129 display->funcs.cdclk->get_cdclk(display, cdclk_config); in intel_cdclk_get_cdclk()
136 display->funcs.cdclk->set_cdclk(display, cdclk_config, pipe); in intel_cdclk_set_cdclk()
335 tmp = intel_de_read(display, display->platform.pineview || in intel_hpll_vco()
1214 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in skl_sanitize_cdclk()
2141 if (DISPLAY_VER(display) >= 14 || display->platform.dg2) in bxt_set_cdclk()
2224 display->cdclk.hw.cdclk == display->cdclk.hw.bypass) in bxt_sanitize_cdclk()
2228 cdclk = bxt_calc_cdclk(display, display->cdclk.hw.cdclk); in bxt_sanitize_cdclk()
3209 intel_atomic_global_obj_init(display, &display->cdclk.obj, in intel_cdclk_init()
3449 display->cdclk.max_cdclk_freq = display->cdclk.hw.cdclk; in intel_update_max_cdclk()
3469 intel_cdclk_get_cdclk(display, &display->cdclk.hw); in intel_update_cdclk()
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| H A D | intel_gmbus.c | 212 intel_de_write(display, GMBUS0(display), 0); in intel_gmbus_reset()
213 intel_de_write(display, GMBUS4(display), 0); in intel_gmbus_reset()
220 intel_de_rmw(display, DSPCLK_GATE_D(display), in pnv_gmbus_clock_gating()
242 struct intel_display *display = bus->display; in get_reserved() local
257 struct intel_display *display = bus->display; in get_clock() local
269 struct intel_display *display = bus->display; in get_data() local
281 struct intel_display *display = bus->display; in set_clock() local
298 struct intel_display *display = bus->display; in set_data() local
458 intel_de_write_fw(display, GMBUS1(display), in gmbus_xfer_read_chunk()
537 intel_de_write_fw(display, GMBUS1(display), in gmbus_xfer_write_chunk()
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| H A D | intel_fifo_underrun.c | 66 for_each_pipe(display, pipe) { in ivb_can_enable_err_int()
84 for_each_pipe(display, pipe) { in cpt_can_enable_serr_int()
126 intel_de_write(display, reg, in i9xx_set_fifo_underrun_reporting()
186 drm_err(display->drm, in ivb_set_fifo_underrun_reporting()
230 intel_de_write(display, SERR_INT, in cpt_check_pch_fifo_underruns()
246 intel_de_write(display, SERR_INT, in cpt_set_fifo_underrun_reporting()
258 drm_err(display->drm, in cpt_set_fifo_underrun_reporting()
277 if (HAS_GMCH(display)) in __intel_set_cpu_fifo_underrun_reporting()
279 else if (display->platform.ironlake || display->platform.sandybridge) in __intel_set_cpu_fifo_underrun_reporting()
388 if (HAS_GMCH(display) && in intel_cpu_fifo_underrun_irq_handler()
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| H A D | intel_combo_phy.c | 99 drm_dbg_kms(display->drm, in check_phy_reg()
141 else if ((display->platform.jasperlake || display->platform.elkhartlake) || in has_phy_misc()
143 display->platform.dg1) in has_phy_misc()
182 drm_err(display->drm, in ehl_vbt_ddi_d_present()
210 else if (display->platform.dg1 || display->platform.rocketlake) in phy_is_master()
242 if (display->platform.jasperlake || display->platform.elkhartlake) { in icl_combo_phy_verify_state()
320 drm_dbg_kms(display->drm, in icl_combo_phys_init()
336 if ((display->platform.jasperlake || display->platform.elkhartlake) && in icl_combo_phys_init()
380 if (display->platform.tigerlake || display->platform.dg1) { in icl_combo_phys_uninit()
386 drm_dbg_kms(display->drm, in icl_combo_phys_uninit()
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| H A D | intel_dmc.c | 653 drm_WARN_ONCE(display->drm, !intel_de_read(display, DMC_HTP_SKL), in assert_dmc_loaded()
684 struct intel_display *display = dmc->display; in dmc_set_fw_offset() local
714 struct intel_display *display = dmc->display; in dmc_mmio_addr_sanity_check() local
747 struct intel_display *display = dmc->display; in parse_dmc_fw_header() local
866 struct intel_display *display = dmc->display; in parse_dmc_fw_package() local
920 struct intel_display *display = dmc->display; in parse_dmc_fw_css() local
942 struct intel_display *display = dmc->display; in parse_dmc_fw() local
995 drm_WARN_ON(display->drm, display->dmc.wakeref); in intel_dmc_runtime_pm_get()
1020 struct intel_display *display = dmc->display; in dmc_load_work_fn() local
1095 dmc->display = display; in intel_dmc_init()
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| H A D | intel_audio.c | 592 if (display->platform.valleyview || display->platform.cherryview) { in ibx_audio_regs_init()
691 if (HAS_DP20(display)) in intel_audio_sdp_split_update()
896 else if (display->platform.valleyview || display->platform.cherryview || in intel_audio_hooks_init()
899 else if (display->platform.haswell || DISPLAY_VER(display) >= 8) in intel_audio_hooks_init()
1012 } else if (DISPLAY_VER(display) == 9 || display->platform.broadwell) { in intel_audio_min_cdclk()
1032 if ((display->platform.valleyview || display->platform.cherryview) && in intel_audio_min_cdclk()
1117 if (drm_WARN_ON_ONCE(display->drm, !HAS_DDI(display))) in intel_audio_component_get_cdclk_freq()
1182 if (!HAS_DDI(display)) in intel_audio_component_sync_audio_rate()
1295 drm_err(display->drm, in intel_audio_component_unbind()
1343 if ((display->platform.tigerlake || display->platform.rocketlake) && in intel_audio_component_init()
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| H A D | intel_de.h | 26 intel_dmc_wl_get(display, reg); in __intel_de_read()
30 intel_dmc_wl_put(display, reg); in __intel_de_read()
41 intel_dmc_wl_get(display, reg); in intel_de_read8()
45 intel_dmc_wl_put(display, reg); in intel_de_read8()
71 intel_dmc_wl_get(display, reg); in __intel_de_posting_read()
75 intel_dmc_wl_put(display, reg); in __intel_de_posting_read()
82 intel_dmc_wl_get(display, reg); in __intel_de_write()
86 intel_dmc_wl_put(display, reg); in __intel_de_write()
103 intel_dmc_wl_get(display, reg); in __intel_de_rmw()
107 intel_dmc_wl_put(display, reg); in __intel_de_rmw()
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| H A D | intel_lpe_audio.c | 80 #define HAS_LPE_AUDIO(display) ((display)->audio.lpe.platdev) argument
134 drm_err(display->drm, in lpe_audio_platdev_create()
189 if (display->platform.valleyview || display->platform.cherryview) { in lpe_audio_detect()
199 drm_info(display->drm, in lpe_audio_detect()
214 display->audio.lpe.irq); in lpe_audio_setup()
219 drm_dbg(display->drm, "irq = %d\n", display->audio.lpe.irq); in lpe_audio_setup()
224 drm_err(display->drm, in lpe_audio_setup()
230 display->audio.lpe.platdev = lpe_audio_platdev_create(display); in lpe_audio_setup()
234 drm_err(display->drm, in lpe_audio_setup()
250 display->audio.lpe.irq = -1; in lpe_audio_setup()
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| H A D | vlv_dsi_regs.h | 14 #define _MIPI_MMIO_BASE(display) ((display)->dsi.mmio_base) argument
107 #define MIPI_INTR_STAT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_STAT,… argument
110 #define MIPI_INTR_EN(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INTR_EN, _MI… argument
209 #define MIPI_HBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HBP_COUNT,… argument
213 #define MIPI_HFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_HFP_COUNT,… argument
225 #define MIPI_VBP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VBP_COUNT,… argument
229 #define MIPI_VFP_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_VFP_COUNT,… argument
248 #define MIPI_DPI_DATA(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_DPI_DATA, _… argument
254 #define MIPI_INIT_COUNT(display, port) _MMIO_MIPI(_MIPI_MMIO_BASE(display), port, _MIPIA_INIT_COUN… argument
392 #define MIPIA_DBI_TYPEC_CTRL(display) (_MIPI_MMIO_BASE(display) + 0xb100) argument
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| H A D | intel_pps.c | 34 if (display->platform.valleyview || display->platform.cherryview) { in pps_name()
280 return intel_de_read(display, PP_STATUS(display, pps_idx)) & PP_ON; in pps_has_pp_on()
356 if (display->platform.valleyview || display->platform.cherryview) in intel_num_pps()
359 if (display->platform.geminilake || display->platform.broxton) in intel_num_pps()
508 if (display->platform.valleyview || display->platform.cherryview) in intel_pps_get_registers()
521 if (display->platform.geminilake || display->platform.broxton || in intel_pps_get_registers()
726 if (drm_WARN_ON(display->drm, !HAS_DDI(display) && in ilk_get_pp_control()
1780 if (!HAS_DISPLAY(display) || HAS_DDI(display)) in intel_pps_unlock_regs_wa()
1789 intel_de_rmw(display, PP_CONTROL(display, pps_idx), in intel_pps_unlock_regs_wa()
1846 if (drm_WARN_ON(display->drm, HAS_DDI(display))) in assert_pps_unlocked()
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| H A D | intel_display_irq.c | 120 struct intel_display *display = &dev_priv->display; in intel_handle_vblank() local
135 struct intel_display *display = &dev_priv->display; in ilk_update_display_irq() local
172 struct intel_display *display = &dev_priv->display; in bdw_update_port_irq() local
206 struct intel_display *display = &dev_priv->display; in bdw_update_pipe_irq() local
249 struct intel_display *display = &dev_priv->display; in ibx_display_interrupt_update() local
324 struct intel_display *display = &dev_priv->display; in i915_enable_pipestat() local
453 struct intel_display *display = &i915->display; in flip_done_handler() local
1335 struct intel_display *display = &i915->display; in gen8_read_and_ack_pch_irqs() local
1522 struct intel_display *display = &i915->display; in gen11_gu_misc_irq_ack() local
1537 struct intel_display *display = &i915->display; in gen11_gu_misc_irq_handler() local
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| H A D | intel_cmtg.c | 66 return DISPLAY_VER(display) >= 20; in intel_cmtg_has_cmtg_b()
71 return DISPLAY_VER(display) >= 14; in intel_cmtg_has_clock_sel()
77 drm_dbg_kms(display->drm, in intel_cmtg_dump_config()
92 if (!HAS_TRANSCODER(display, trans)) in intel_cmtg_transcoder_is_secondary()
98 val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, trans)); in intel_cmtg_transcoder_is_secondary()
111 if (intel_cmtg_has_cmtg_b(display)) { in intel_cmtg_get_config()
123 if (DISPLAY_VER(display) >= 20) in intel_cmtg_disable_requires_modeset()
136 intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_A), in intel_cmtg_disable()
140 intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_B), in intel_cmtg_disable()
173 if (!HAS_CMTG(display)) in intel_cmtg_sanitize()
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| H A D | intel_fbc.c | 271 struct intel_display *display = fbc->display; in i8xx_fbc_ctl() local
313 struct intel_display *display = fbc->display; in i8xx_fbc_deactivate() local
334 struct intel_display *display = fbc->display; in i8xx_fbc_activate() local
366 struct intel_display *display = fbc->display; in i8xx_fbc_nuke() local
376 struct intel_display *display = fbc->display; in i8xx_fbc_program_cfb() local
404 struct intel_display *display = fbc->display; in i965_fbc_nuke() local
438 struct intel_display *display = fbc->display; in g4x_dpfc_ctl() local
460 struct intel_display *display = fbc->display; in g4x_fbc_activate() local
472 struct intel_display *display = fbc->display; in g4x_fbc_deactivate() local
495 struct intel_display *display = fbc->display; in g4x_fbc_program_cfb() local
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| H A D | intel_dmc_wl.c | 159 struct intel_dmc_wl *wl = &display->wl; in __intel_dmc_wl_release()
171 struct intel_display *display = in intel_dmc_wl_work() local
285 return display->params.enable_dmc_wl; in __intel_dmc_wl_supported()
292 if (!HAS_DMC_WAKELOCK(display)) { in intel_dmc_wl_sanitize_param()
295 if (DISPLAY_VER(display) >= 30) in intel_dmc_wl_sanitize_param()
303 drm_WARN_ON(display->drm, in intel_dmc_wl_sanitize_param()
333 intel_dmc_wl_sanitize_param(display); in intel_dmc_wl_init()
335 if (!display->params.enable_dmc_wl) in intel_dmc_wl_init()
384 __intel_dmc_wl_take(display); in intel_dmc_wl_enable()
464 __intel_dmc_wl_take(display); in intel_dmc_wl_get()
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| H A D | i9xx_plane.c | 118 if (display->platform.broadwell || display->platform.haswell) in i9xx_plane_has_fbc()
145 else if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in i9xx_plane_has_windowing()
164 if (display->platform.g4x || display->platform.ironlake || in i9xx_plane_ctl()
446 intel_de_write_fw(display, DSPPOS(display, i9xx_plane), in i9xx_plane_update_noarm()
448 intel_de_write_fw(display, DSPSIZE(display, i9xx_plane), in i9xx_plane_update_noarm()
484 intel_de_write_fw(display, PRIMPOS(display, i9xx_plane), in i9xx_plane_update_arm()
611 intel_de_write_fw(display, DSPSURF(display, i9xx_plane), in g4x_primary_async_flip()
923 if (HAS_FBC(display) && DISPLAY_VER(display) < 4 && in intel_primary_plane_create()
1013 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in intel_primary_plane_create()
1047 if (DISPLAY_VER(display) >= 5 || display->platform.g4x) in intel_primary_plane_create()
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| H A D | intel_vrr.c | 363 intel_de_rmw(display, CHICKEN_TRANS(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
373 intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
375 intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
383 intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
385 intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
387 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
472 intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), in intel_vrr_enable()
476 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_enable()
480 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_enable()
493 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_disable()
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| H A D | vlv_dsi.c | 173 intel_de_write(display, MIPI_INTR_STAT(display, port), in intel_dsi_host_transfer()
347 intel_de_rmw(display, MIPI_CTRL(display, port), in glk_dsi_enable_io()
386 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
391 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
400 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
516 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_enter_low_power_mode()
625 intel_de_rmw(display, MIPI_CTRL(display, port), in intel_dsi_port_enable()
1337 intel_de_write(display, MIPI_CTRL(display, PORT_A), in intel_dsi_prepare()
1343 intel_de_write(display, MIPI_CTRL(display, port), in intel_dsi_prepare()
1348 intel_de_rmw(display, MIPI_CTRL(display, port), in intel_dsi_prepare()
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| /linux-6.15/drivers/gpu/drm/xe/display/ |
| H A D | xe_display.c | 114 struct intel_display *display = &xe->display; in xe_display_fini_early() local
127 struct intel_display *display = &xe->display; in xe_display_init_early() local
174 struct intel_display *display = &xe->display; in xe_display_fini() local
184 struct intel_display *display = &xe->display; in xe_display_init() local
199 struct intel_display *display = &xe->display; in xe_display_register() local
210 struct intel_display *display = &xe->display; in xe_display_unregister() local
232 struct intel_display *display = &xe->display; in xe_display_irq_enable() local
290 struct intel_display *display = &xe->display; in xe_display_enable_d3cold() local
313 struct intel_display *display = &xe->display; in xe_display_disable_d3cold() local
337 struct intel_display *display = &xe->display; in xe_display_pm_suspend() local
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| /linux-6.15/drivers/gpu/drm/i915/ |
| H A D | Makefile | 222 display/hsw_ips.o \
225 display/i9xx_wm.o \
231 display/intel_bo.o \
232 display/intel_bw.o \
263 display/intel_fb.o \
292 display/intel_tc.o \
295 display/intel_wm.o \
314 display/dvo_ivch.o \
318 display/g4x_dp.o \
320 display/icl_dsi.o \
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| /linux-6.15/drivers/gpu/drm/xe/ |
| H A D | Makefile | 164 -I$(src)/display/ext \
175 $(obj)/i915-display/%.o: $(srctree)/drivers/gpu/drm/i915/display/%.c FORCE
181 display/ext/i915_irq.o \
183 display/intel_bo.o \
184 display/intel_fb_bo.o \
186 display/xe_display.o \
189 display/xe_display_wa.o \
191 display/xe_fb_pin.o \
192 display/xe_hdcp_gsc.o \
194 display/xe_tdf.o
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