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Searched refs:cache_line_size (Results 1 – 25 of 76) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_crat.c59 .cache_line_size = 64,
69 .cache_line_size = 64,
79 .cache_line_size = 64,
95 .cache_line_size = 64,
105 .cache_line_size = 64,
115 .cache_line_size = 64,
145 .cache_line_size = 64,
155 .cache_line_size = 64,
165 .cache_line_size = 64,
175 .cache_line_size = 64,
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H A Dkfd_crat.h168 uint16_t cache_line_size; member
304 uint32_t cache_line_size; member
/linux-6.15/arch/mips/mm/
H A Dpage.c87 static int cache_line_size; variable
217 max(cache_line_size >> 1, in set_prefetch_parameters()
299 off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size) in build_clear_page()
300 * cache_line_size : 0; in build_clear_page()
303 off -= cache_line_size; in build_clear_page()
452 off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) * in build_copy_page()
453 cache_line_size : 0; in build_copy_page()
456 off -= cache_line_size; in build_copy_page()
458 off = cache_line_size ? min(8, pref_bias_copy_store / cache_line_size) * in build_copy_page()
459 cache_line_size : 0; in build_copy_page()
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/linux-6.15/tools/perf/util/
H A Dcacheline.c6 #define cache_line_size(cacheline_sizep) *cacheline_sizep = sysconf(_SC_LEVEL1_DCACHE_LINESIZE) macro
10 static void cache_line_size(int *cacheline_sizep) in cache_line_size() function
22 cache_line_size(&size); in cacheline_size()
/linux-6.15/arch/parisc/include/asm/
H A Dcache.h31 #define cache_line_size() dcache_stride macro
32 #define dma_get_cache_alignment cache_line_size
/linux-6.15/drivers/net/ethernet/mellanox/mlx5/core/
H A Dalloc.c136 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_alloc_db_pgdir()
165 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_alloc_db_from_pgdir()
177 offset = db->index * cache_line_size(); in mlx5_alloc_db_from_pgdir()
218 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_db_free()
/linux-6.15/arch/arm64/include/asm/
H A Dcache.h86 int cache_line_size(void);
88 #define dma_get_cache_alignment cache_line_size
/linux-6.15/arch/arm64/kernel/
H A Dcacheinfo.c15 int cache_line_size(void) in cache_line_size() function
22 EXPORT_SYMBOL_GPL(cache_line_size);
/linux-6.15/arch/arm/kernel/
H A Dcacheinfo.c51 int cache_line_size(void) in cache_line_size() function
62 EXPORT_SYMBOL_GPL(cache_line_size);
/linux-6.15/drivers/s390/cio/
H A Dairq.c140 if ((cache_line_size() * BITS_PER_BYTE) < bits in airq_iv_create()
307 cache_line_size(), in airq_init()
308 cache_line_size(), PAGE_SIZE); in airq_init()
/linux-6.15/arch/arm/include/asm/
H A Dcache.h31 int cache_line_size(void);
/linux-6.15/drivers/infiniband/sw/rxe/
H A Drxe_queue.c77 if (elem_size < cache_line_size()) in rxe_queue_init()
78 elem_size = cache_line_size(); in rxe_queue_init()
/linux-6.15/tools/testing/selftests/vDSO/
H A Dvdso_test_getrandom.c66 size_t state_size_aligned, cache_line_size = sysconf(_SC_LEVEL1_DCACHE_LINESIZE) ?: 1; in vgetrandom_get_state() local
69 …ate_size_aligned = (vgrnd.params.size_of_opaque_state + cache_line_size - 1) & (~(cache_line_size … in vgetrandom_get_state()
/linux-6.15/arch/um/include/asm/
H A Dprocessor-generic.h86 #define cache_line_size() (boot_cpu_data.cache_alignment) macro
/linux-6.15/arch/arc/include/asm/
H A Dcache.h51 #define cache_line_size() SMP_CACHE_BYTES macro
/linux-6.15/Documentation/PCI/endpoint/function/binding/
H A Dpci-test.rst18 cache_line_size don't care
H A Dpci-ntb.rst18 cache_line_size don't care
/linux-6.15/include/linux/
H A Dcache.h104 #define cache_line_size() L1_CACHE_BYTES macro
H A Dpci-epf.h51 u8 cache_line_size; member
/linux-6.15/drivers/staging/vc04_services/interface/vchiq_arm/
H A Dvchiq_arm.h34 unsigned int cache_line_size; member
/linux-6.15/drivers/infiniband/hw/hfi1/
H A Dmmu_rb.c51 free_ptr = kzalloc(sizeof(*h) + cache_line_size() - 1, GFP_KERNEL); in hfi1_mmu_rb_register()
55 h = PTR_ALIGN(free_ptr, cache_line_size()); in hfi1_mmu_rb_register()
/linux-6.15/Documentation/PCI/endpoint/
H A Dpci-endpoint-cfs.rst68 ... cache_line_size
132 | cache_line_size
/linux-6.15/drivers/pci/endpoint/
H A Dpci-ep-cfs.c437 PCI_EPF_HEADER_R(cache_line_size)
438 PCI_EPF_HEADER_W_u8(cache_line_size)
455 CONFIGFS_ATTR(pci_epf_, cache_line_size);
/linux-6.15/tools/virtio/ringtest/
H A Dptr_ring.c14 #define cache_line_size() SMP_CACHE_BYTES macro
/linux-6.15/drivers/pci/
H A Dpci-bridge-emul.h14 u8 cache_line_size; member

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