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Revision tags: v6.15, v6.15-rc7, v6.15-rc6, v6.15-rc5, v6.15-rc4, v6.15-rc3, v6.15-rc2, v6.15-rc1, v6.14, v6.14-rc7, v6.14-rc6, v6.14-rc5, v6.14-rc4, v6.14-rc3, v6.14-rc2, v6.14-rc1, v6.13 |
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f520fab5 |
| 17-Jan-2025 |
Dmitry Baryshkov <[email protected]> |
ARM: 9440/1: cacheinfo fix format field mask
Fix C&P error left unnoticed during the reviews. The FORMAT field spans
over bits 29-31, not 24-27 of the CTR register.
Closes: https://lore.kernel.org/
ARM: 9440/1: cacheinfo fix format field mask
Fix C&P error left unnoticed during the reviews. The FORMAT field spans
over bits 29-31, not 24-27 of the CTR register.
Closes: https://lore.kernel.org/linux-arm-msm/[email protected]/
Fixes: a9ff94477836 ("ARM: 9433/2: implement cacheinfo support")
Reported-by: Marek Szyprowski <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Russell King (Oracle) <[email protected]>
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a9ff9447 |
| 14-Jan-2025 |
Dmitry Baryshkov <[email protected]> |
ARM: 9433/2: implement cacheinfo support
On ARMv7 / v7m machines read CTR and CLIDR registers to provide
information regarding the cache topology. Earlier machines should
describe full cache topolog
ARM: 9433/2: implement cacheinfo support
On ARMv7 / v7m machines read CTR and CLIDR registers to provide
information regarding the cache topology. Earlier machines should
describe full cache topology in the device tree.
Note, this follows the ARM64 cacheinfo support and provides only minimal
support required to bootstrap cache info. All useful properties should
be decribed in Device Tree.
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Russell King (Oracle) <[email protected]>
show more ...
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