Searched refs:WRITE_DATA_DST_SEL (Results 1 – 18 of 18) sorted by relevance
144 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
142 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
269 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
130 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
107 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
892 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v8_0_ring_test_ib()5146 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5154 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5162 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()5170 WRITE_DATA_DST_SEL(0))); in gfx_v8_0_ring_emit_gds_switch()6256 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()6265 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v8_0_ring_emit_fence_kiq()7232 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_ce_meta()7265 WRITE_DATA_DST_SEL(8) | in gfx_v8_0_ring_emit_de_meta()
3183 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_wreg()4013 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4021 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4029 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()4037 WRITE_DATA_DST_SEL(0))); in gfx_v7_0_ring_emit_gds_switch()
376 WRITE_DATA_DST_SEL(0) | in gfx_v9_4_3_write_data_to_reg()470 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_4_3_ring_test_ib()2928 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_4_3_ring_emit_fence_kiq()2937 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_4_3_ring_emit_fence_kiq()
482 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v11_0_write_data_to_reg()613 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v11_0_ring_test_ib()5837 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()5846 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v11_0_ring_emit_fence_kiq()5942 amdgpu_ring_write(ring, WRITE_DATA_DST_SEL(5) | WR_CONFIRM); in gfx_v11_0_ring_emit_gfx_shadow()6068 WRITE_DATA_DST_SEL(8) | in gfx_v11_0_ring_emit_de_meta()
1138 WRITE_DATA_DST_SEL(0) | in gfx_v9_0_write_data_to_reg()1221 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v9_0_ring_test_ib()5643 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5652 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v9_0_ring_emit_fence_kiq()5691 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_ce_meta()5804 WRITE_DATA_DST_SEL(8) | in gfx_v9_0_ring_emit_de_meta()
1409 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3976 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0)); in gfx_v10_0_write_data_to_reg()4069 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v10_0_ring_test_ib()8756 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8765 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v10_0_ring_emit_fence_kiq()8892 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_ce_meta()8928 WRITE_DATA_DST_SEL(8) | in gfx_v10_0_ring_emit_de_meta()
508 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; in gfx_v12_0_ring_test_ib()4439 WRITE_DATA_DST_SEL(5) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()4448 WRITE_DATA_DST_SEL(0) | WR_CONFIRM)); in gfx_v12_0_ring_emit_fence_kiq()
2341 WRITE_DATA_DST_SEL(0))); in gfx_v6_0_ring_emit_wreg()
1637 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
3742 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()5684 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5698 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5705 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5716 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()5727 WRITE_DATA_DST_SEL(0))); in cik_vm_flush()
1728 #define WRITE_DATA_DST_SEL(x) ((x) << 8) macro
5062 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5077 WRITE_DATA_DST_SEL(0))); in si_vm_flush()5085 WRITE_DATA_DST_SEL(0))); in si_vm_flush()