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Searched refs:WREG32_PCIE (Results 1 – 25 of 26) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v6_1.c188 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v6_1_update_medium_grain_clock_gating()
208 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v6_1_update_medium_grain_light_sleep()
277 WREG32_PCIE(smnPCIE_CI_CNTL, data); in nbio_v6_1_init_registers()
290 WREG32_PCIE(smnRCC_BIF_STRAP2, data); in nbio_v6_1_program_ltr()
314 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v6_1_program_aspm()
319 WREG32_PCIE(smnPCIE_LC_CNTL7, data); in nbio_v6_1_program_aspm()
329 WREG32_PCIE(smnPCIE_LC_CNTL3, data); in nbio_v6_1_program_aspm()
335 WREG32_PCIE(smnRCC_BIF_STRAP3, data); in nbio_v6_1_program_aspm()
360 WREG32_PCIE(smnPCIE_LC_CNTL6, data); in nbio_v6_1_program_aspm()
383 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v6_1_program_aspm()
[all …]
H A Dnbio_v7_4.c271 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_4_update_medium_grain_light_sleep()
685 WREG32_PCIE(smnRCC_BIF_STRAP2, data); in nbio_v7_4_program_ltr()
712 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v7_4_program_aspm()
717 WREG32_PCIE(smnPCIE_LC_CNTL7, data); in nbio_v7_4_program_aspm()
727 WREG32_PCIE(smnPCIE_LC_CNTL3, data); in nbio_v7_4_program_aspm()
733 WREG32_PCIE(smnRCC_BIF_STRAP3, data); in nbio_v7_4_program_aspm()
738 WREG32_PCIE(smnRCC_BIF_STRAP5, data); in nbio_v7_4_program_aspm()
758 WREG32_PCIE(smnPCIE_LC_CNTL6, data); in nbio_v7_4_program_aspm()
769 WREG32_PCIE(smnRCC_BIF_STRAP3, data); in nbio_v7_4_program_aspm()
781 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v7_4_program_aspm()
[all …]
H A Dnbio_v2_3.c254 WREG32_PCIE(smnCPM_CONTROL, data); in nbio_v2_3_update_medium_grain_clock_gating()
277 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v2_3_update_medium_grain_light_sleep()
340 WREG32_PCIE(smnPCIE_CONFIG_CNTL, data); in nbio_v2_3_init_registers()
376 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v2_3_enable_aspm()
413 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v2_3_program_aspm()
418 WREG32_PCIE(smnPCIE_LC_CNTL7, data); in nbio_v2_3_program_aspm()
428 WREG32_PCIE(smnPCIE_LC_CNTL3, data); in nbio_v2_3_program_aspm()
459 WREG32_PCIE(smnPCIE_LC_CNTL6, data); in nbio_v2_3_program_aspm()
485 WREG32_PCIE(smnPCIE_LC_CNTL, data); in nbio_v2_3_program_aspm()
490 WREG32_PCIE(smnPCIE_LC_CNTL3, data); in nbio_v2_3_program_aspm()
[all …]
H A Dumc_v6_1.c56 WREG32_PCIE(rsmu_umc_addr * 4, rsmu_umc_val); in umc_v6_1_enable_umc_index_mode()
71 WREG32_PCIE(rsmu_umc_addr * 4, rsmu_umc_val); in umc_v6_1_disable_umc_index_mode()
124 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
128 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
137 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
141 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_1_clear_error_count_per_channel()
200 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_query_correctable_error_count()
210 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_query_correctable_error_count()
418 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_1_err_cnt_init_per_channel()
420 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V6_1_CE_CNT_INIT); in umc_v6_1_err_cnt_init_per_channel()
[all …]
H A Dumc_v8_7.c197 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
201 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
210 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
214 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_7_clear_error_count_per_channel()
255 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_query_correctable_error_count()
265 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_query_correctable_error_count()
408 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_err_cnt_init_per_channel()
410 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_7_CE_CNT_INIT); in umc_v8_7_err_cnt_init_per_channel()
415 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_7_err_cnt_init_per_channel()
416 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_7_CE_CNT_INIT); in umc_v8_7_err_cnt_init_per_channel()
H A Dcik.c1622 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1626 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1656 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); in cik_pcie_gen3_enable()
1706 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); in cik_program_aspm()
1711 WREG32_PCIE(ixPCIE_LC_CNTL3, data); in cik_program_aspm()
1716 WREG32_PCIE(ixPCIE_P_CNTL, data); in cik_program_aspm()
1729 WREG32_PCIE(ixPCIE_LC_CNTL, data); in cik_program_aspm()
1789 WREG32_PCIE(ixPCIE_LC_CNTL2, data); in cik_program_aspm()
1826 WREG32_PCIE(ixPCIE_LC_CNTL, data); in cik_program_aspm()
1834 WREG32_PCIE(ixPCIE_CNTL2, data); in cik_program_aspm()
[all …]
H A Dumc_v8_14.c49 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_14_clear_error_count_per_channel()
138 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_14_err_cnt_init_per_channel()
140 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_14_CE_CNT_INIT); in umc_v8_14_err_cnt_init_per_channel()
H A Dumc_v6_7.c284 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_7_query_correctable_error_count()
294 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v6_7_query_correctable_error_count()
383 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
387 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
396 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
400 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v6_7_reset_error_count_per_channel()
H A Dvi.c1118 WREG32_PCIE(ixPCIE_LC_CNTL, data); in vi_enable_aspm()
1138 WREG32_PCIE(ixPCIE_LC_CNTL, data); in vi_program_aspm()
1150 WREG32_PCIE(ixPCIE_LC_CNTL3, data); in vi_program_aspm()
1155 WREG32_PCIE(ixPCIE_P_CNTL, data); in vi_program_aspm()
1175 WREG32_PCIE(ixPCIE_LC_CNTL6, data); in vi_program_aspm()
1223 WREG32_PCIE(ixCPM_CONTROL, data); in vi_program_aspm()
1239 WREG32_PCIE(ixPCIE_LC_CNTL7, data); in vi_program_aspm()
1244 WREG32_PCIE(ixPCIE_HW_DEBUG, data); in vi_program_aspm()
1252 WREG32_PCIE(ixPCIE_LC_CNTL2, data); in vi_program_aspm()
1266 WREG32_PCIE(ixPCIE_LC_CNTL, data); in vi_program_aspm()
[all …]
H A Dumc_v8_10.c91 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, in umc_v8_10_clear_error_count_per_channel()
313 WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel); in umc_v8_10_err_cnt_init_per_channel()
315 WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_10_CE_CNT_INIT); in umc_v8_10_err_cnt_init_per_channel()
H A Dnbio_v7_0.c161 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data); in nbio_v7_0_update_medium_grain_clock_gating()
203 WREG32_PCIE(smnPCIE_CNTL2, data); in nbio_v7_0_update_medium_grain_light_sleep()
H A Dsoc15.c772 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK, perfctr); in soc15_get_pcie_usage()
778 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); in soc15_get_pcie_usage()
787 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); in soc15_get_pcie_usage()
821 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctr); in vega20_get_pcie_usage()
827 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000005); in vega20_get_pcie_usage()
836 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000002); in vega20_get_pcie_usage()
H A Dsi.c1599 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); in si_get_pcie_usage()
1605 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); in si_get_pcie_usage()
1614 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); in si_get_pcie_usage()
2435 WREG32_PCIE(PCIE_P_CNTL, data); in si_program_aspm()
2598 WREG32_PCIE(PCIE_CNTL2, data); in si_program_aspm()
H A Damdgpu_cgs.c92 return WREG32_PCIE(index, value); in amdgpu_cgs_write_ind_register()
H A Damdgpu_xgmi.c1238 WREG32_PCIE(pcs_status_reg, 0xFFFFFFFF); in pcs_clear_status()
1239 WREG32_PCIE(pcs_status_reg, 0); in pcs_clear_status()
H A Dgmc_v7_0.c878 WREG32_PCIE(ixPCIE_CNTL2, data); in gmc_v7_0_enable_bif_mgls()
H A Damdgpu.h1335 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) macro
H A Damdgpu_debugfs.c610 WREG32_PCIE(*pos, value); in amdgpu_debugfs_regs_pcie_write()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dr300.c97 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_tlb_flush()
166 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable()
169 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp); in rv370_pcie_gart_enable()
170 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_enable()
171 WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0); in rv370_pcie_gart_enable()
178 WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0); in rv370_pcie_gart_enable()
182 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp); in rv370_pcie_gart_enable()
195 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, 0); in rv370_pcie_gart_disable()
196 WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, 0); in rv370_pcie_gart_disable()
197 WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0); in rv370_pcie_gart_disable()
[all …]
H A Dsi.c5562 WREG32_PCIE(PCIE_CNTL2, data); in si_enable_bif_mgls()
7250 WREG32_PCIE(PCIE_P_CNTL, data); in si_program_aspm()
7413 WREG32_PCIE(PCIE_CNTL2, data); in si_program_aspm()
H A Drv6xx_dpm.c135 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv6xx_enable_pll_sleep_in_l1()
H A Drv770_dpm.c128 WREG32_PCIE(PCIE_P_CNTL, tmp); in rv770_enable_pll_sleep_in_l1()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0.c155 WREG32_PCIE(addr_start, src[i]); in smu_v13_0_load_microcode()
159 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v13_0_load_microcode()
161 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v13_0_load_microcode()
2543 WREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff), 0); in smu_v13_0_disable_pmfw_state()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0.c130 WREG32_PCIE(addr_start, src[i]); in smu_v14_0_load_microcode()
134 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v14_0_load_microcode()
136 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v14_0_load_microcode()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c156 WREG32_PCIE(addr_start, src[i]); in smu_v11_0_load_microcode()
160 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v11_0_load_microcode()
162 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff), in smu_v11_0_load_microcode()

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