Home
last modified time | relevance | path

Searched refs:WREG32_FIELD (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v3_0.c165 WREG32_FIELD(VCE_RB_ARB_CTRL, VCE_CGTT_OVERRIDE, override ? 1 : 0); in vce_v3_0_override_vce_clock_gating()
249 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); in vce_v3_0_firmware_loaded()
251 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); in vce_v3_0_firmware_loaded()
303 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 1); in vce_v3_0_start()
308 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1); in vce_v3_0_start()
310 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); in vce_v3_0_start()
316 WREG32_FIELD(VCE_STATUS, JOB_BUSY, 0); in vce_v3_0_start()
345 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 0); in vce_v3_0_stop()
348 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); in vce_v3_0_stop()
597 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1); in vce_v3_0_mc_resume()
[all …]
H A Dvce_v2_0.c201 WREG32_FIELD(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, 1); in vce_v2_0_mc_resume()
257 WREG32_FIELD(VCE_VCPU_CNTL, CLK_EN, 1); in vce_v2_0_start()
258 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 1); in vce_v2_0_start()
260 WREG32_FIELD(VCE_SOFT_RESET, ECPU_SOFT_RESET, 0); in vce_v2_0_start()
542 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1); in vce_v2_0_soft_reset()
H A Dgfx_v8_0.c3749 WREG32_FIELD(GRBM_CNTL, READ_TIMEOUT, 0xFF); in gfx_v8_0_constants_init()
3966 WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1); in gfx_v8_0_init_save_restore_list()
4005 WREG32_FIELD(RLC_SRM_CNTL, SRM_ENABLE, 1); in gfx_v8_0_enable_save_restore_machine()
4065 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 0); in gfx_v8_0_rlc_stop()
4073 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v8_0_rlc_reset()
4076 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v8_0_rlc_reset()
4082 WREG32_FIELD(RLC_CNTL, RLC_ENABLE_F32, 1); in gfx_v8_0_rlc_start()
4578 WREG32_FIELD(CP_PQ_WPTR_POLL_CNTL, EN, 0); in gfx_v8_0_mqd_commit()
4681 WREG32_FIELD(CP_PQ_STATUS, DOORBELL_ENABLE, 1); in gfx_v8_0_set_mec_doorbell_range()
5615 WREG32_FIELD(CP_MEM_SLP_CNTL, CP_MEM_LS_EN, 1); in gfx_v8_0_update_medium_grain_clock_gating()
[all …]
H A Duvd_v6_0.c742 WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0); in uvd_v6_0_start()
745 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 1); in uvd_v6_0_start()
761 WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_UVD, 0); in uvd_v6_0_start()
796 WREG32_FIELD(UVD_LMI_CTRL2, STALL_ARB_UMC, 0); in uvd_v6_0_start()
816 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 1); in uvd_v6_0_start()
818 WREG32_FIELD(UVD_SOFT_RESET, VCPU_SOFT_RESET, 0); in uvd_v6_0_start()
863 WREG32_FIELD(UVD_RBC_RB_CNTL, RB_NO_FETCH, 0); in uvd_v6_0_start()
H A Dgfx_v6_0.c2405 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v6_0_enable_lbpw()
2474 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); in gfx_v6_0_rlc_reset()
2476 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); in gfx_v6_0_rlc_reset()
2749 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1); in gfx_v6_0_enable_gfx_cgpg()
2750 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1); in gfx_v6_0_enable_gfx_cgpg()
2752 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0); in gfx_v6_0_enable_gfx_cgpg()
2802 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1); in gfx_v6_0_init_gfx_cgpg()
H A Damdgpu_amdkfd_gfx_v8.c408 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0); in kgd_hqd_destroy()
H A Duvd_v3_1.c211 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); in uvd_v3_1_set_dcm()
H A Duvd_v4_2.c640 WREG32_FIELD(UVD_CGC_GATE, REGS, 0); in uvd_v4_2_set_dcm()
H A Damdgpu.h1393 #define WREG32_FIELD(reg, field, val) \ macro
/linux-6.15/drivers/accel/habanalabs/common/
H A Dhabanalabs.h2614 #define WREG32_FIELD(reg, offset, field, val) \ macro
/linux-6.15/drivers/accel/habanalabs/goya/
H A Dgoya.c1799 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, offset, in goya_init_golden_registers()
/linux-6.15/drivers/accel/habanalabs/gaudi/
H A Dgaudi.c2531 WREG32_FIELD(TPC0_CFG_MSS_CONFIG, tpc_offset, in gaudi_init_golden_registers()