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Searched refs:RREG32_SMC (Results 1 – 25 of 26) sorted by relevance

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/linux-6.15/drivers/gpu/drm/radeon/
H A Dci_smc.c116 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_start_smc()
124 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_reset_smc()
139 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_stop_smc_clock()
148 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_start_smc_clock()
157 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_is_smc_running()
158 u32 pc_c = RREG32_SMC(SMC_PC_C); in ci_is_smc_running()
176 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
H A Dsi_smc.c115 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_start_smc()
131 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_reset_smc()
145 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_stop_smc_clock()
154 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_start_smc_clock()
163 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_is_smc_running()
164 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_is_smc_running()
202 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_wait_for_smc_inactive()
H A Dtrinity_dpm.c330 value = RREG32_SMC(GFX_POWER_GATING_CNTL); in trinity_gfx_powergating_initialize()
474 value = RREG32_SMC(PM_I_CNTL_1); in trinity_gfx_dynamic_mgpg_enable()
479 value = RREG32_SMC(SMU_S_PG_CNTL); in trinity_gfx_dynamic_mgpg_enable()
484 value = RREG32_SMC(SMU_S_PG_CNTL); in trinity_gfx_dynamic_mgpg_enable()
488 value = RREG32_SMC(PM_I_CNTL_1); in trinity_gfx_dynamic_mgpg_enable()
708 u32 value = RREG32_SMC(SMU_SCLK_DPM_CNTL); in trinity_start_dpm()
837 u32 tp = RREG32_SMC(PM_TP); in trinity_setup_uvd_dpm_interval()
960 u32 value = RREG32_SMC(SMU_SCLK_DPM_TTT); in trinity_program_ttt()
980 u32 tp = RREG32_SMC(PM_TP); in trinity_program_sclk_dpm()
989 value = RREG32_SMC(PM_I_CNTL_1); in trinity_program_sclk_dpm()
[all …]
H A Dci_dpm.c856 tmp = RREG32_SMC(CG_THERMAL_INT); in ci_thermal_set_temperature_range()
864 tmp = RREG32_SMC(CG_THERMAL_CTRL); in ci_thermal_set_temperature_range()
1374 tmp = RREG32_SMC(GENERAL_PWRMGT); in ci_set_dpm_event_sources()
1381 tmp = RREG32_SMC(GENERAL_PWRMGT); in ci_set_dpm_event_sources()
1491 tmp = RREG32_SMC(GENERAL_PWRMGT); in ci_start_dpm()
1552 tmp = RREG32_SMC(GENERAL_PWRMGT); in ci_stop_dpm()
1833 RREG32_SMC(CG_SPLL_FUNC_CNTL); in ci_read_clock_registers()
1835 RREG32_SMC(CG_SPLL_FUNC_CNTL_2); in ci_read_clock_registers()
1837 RREG32_SMC(CG_SPLL_FUNC_CNTL_3); in ci_read_clock_registers()
1839 RREG32_SMC(CG_SPLL_FUNC_CNTL_4); in ci_read_clock_registers()
[all …]
H A Dkv_smc.c60 *enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0); in kv_dpm_get_enable_mask()
H A Dkv_dpm.c173 data = RREG32_SMC(config_regs->offset); in kv_program_pt_config_registers()
487 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); in kv_start_dpm()
502 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_start_am()
512 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_reset_am()
1018 thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL); in kv_enable_thermal_int()
2237 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1); in kv_program_nbps_index_settings()
2264 tmp = RREG32_SMC(CG_THERMAL_INT_CTRL); in kv_set_thermal_temperature_range()
2602 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> in kv_dpm_debugfs_print_current_performance_level()
2611 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> in kv_dpm_debugfs_print_current_performance_level()
2625 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> in kv_dpm_get_current_sclk()
H A Dcik.c224 temp = RREG32_SMC(0xC0300E0C); in kv_get_temp()
1713 if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE) in cik_get_xclk()
9419 tmp = RREG32_SMC(cntl_reg); in cik_set_uvd_clock()
9425 if (RREG32_SMC(status_reg) & DCLK_STATUS) in cik_set_uvd_clock()
9459 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) in cik_set_vce_clocks()
9466 tmp = RREG32_SMC(CG_ECLK_CNTL); in cik_set_vce_clocks()
9472 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) in cik_set_vce_clocks()
9738 orig = data = RREG32_SMC(THM_CLK_CNTL); in cik_program_aspm()
9744 orig = data = RREG32_SMC(MISC_CLK_CTRL); in cik_program_aspm()
9750 orig = data = RREG32_SMC(CG_CLKPIN_CNTL); in cik_program_aspm()
[all …]
H A Dradeon.h2523 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) macro
2555 uint32_t tmp_ = RREG32_SMC(reg); \
H A Dni.c856 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff; in tn_get_temp()
H A Dsi.c7444 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) in si_vce_send_vcepll_ctlreq()
H A Dsi_dpm.c2686 data = RREG32_SMC(offset); in si_program_cac_config_registers()
/linux-6.15/drivers/gpu/drm/amd/pm/legacy-dpm/
H A Dsi_smc.c113 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in amdgpu_si_start_smc()
129 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL) | in amdgpu_si_reset_smc()
143 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in amdgpu_si_smc_clock()
155 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in amdgpu_si_is_smc_running()
156 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in amdgpu_si_is_smc_running()
194 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in amdgpu_si_wait_for_smc_inactive()
H A Dkv_dpm.c416 data = RREG32_SMC(config_regs->offset); in kv_program_pt_config_registers()
717 u32 tmp = RREG32_SMC(ixGENERAL_PWRMGT); in kv_start_dpm()
732 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); in kv_start_am()
743 u32 sclk_pwrmgt_cntl = RREG32_SMC(ixSCLK_PWRMGT_CNTL); in kv_reset_am()
2499 nbdpmconfig1 = RREG32_SMC(ixNB_DPM_CONFIG_1); in kv_program_nbps_index_settings()
2528 tmp = RREG32_SMC(ixCG_THERMAL_INT_CTRL); in kv_set_thermal_temperature_range()
2860 (RREG32_SMC(ixTARGET_AND_CURRENT_PROFILE_INDEX) & in kv_dpm_debugfs_print_current_performance_level()
2870 tmp = (RREG32_SMC(ixSMU_VOLTAGE_STATUS) & in kv_dpm_debugfs_print_current_performance_level()
2945 temp = RREG32_SMC(0xC0300E0C); in kv_dpm_get_temp()
3126 cg_thermal_int = RREG32_SMC(ixCG_THERMAL_INT_CTRL); in kv_dpm_set_interrupt_state()
[all …]
H A Dkv_smc.c63 *enable_mask = RREG32_SMC(ixSMC_SYSCON_MSG_ARG_0); in amdgpu_kv_dpm_get_enable_mask()
H A Dsi_dpm.c2846 data = RREG32_SMC(offset); in si_program_cac_config_registers()
7557 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state()
7562 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state()
7574 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state()
7579 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dcik.c982 rom_cntl = RREG32_SMC(ixROM_CNTL); in cik_read_disabled_bios()
1464 tmp = RREG32_SMC(cntl_reg); in cik_set_uvd_clock()
1471 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) in cik_set_uvd_clock()
1513 tmp = RREG32_SMC(ixCG_ECLK_CNTL); in cik_set_vce_clocks()
1791 orig = data = RREG32_SMC(ixTHM_CLK_CNTL); in cik_program_aspm()
1799 orig = data = RREG32_SMC(ixMISC_CLK_CTRL); in cik_program_aspm()
1807 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL); in cik_program_aspm()
1812 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2); in cik_program_aspm()
1817 orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL); in cik_program_aspm()
1939 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in cik_need_reset_on_init()
[all …]
H A Dvi.c555 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); in vi_get_xclk()
559 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL); in vi_get_xclk()
605 rom_cntl = RREG32_SMC(ixROM_CNTL); in vi_read_disabled_bios()
994 tmp = RREG32_SMC(cntl_reg); in vi_set_uvd_clock()
1005 tmp = RREG32_SMC(status_reg); in vi_set_uvd_clock()
1081 if (RREG32_SMC(reg_status) & status_mask) in vi_set_vce_clocks()
1089 tmp = RREG32_SMC(reg_ctrl); in vi_set_vce_clocks()
1095 if (RREG32_SMC(reg_status) & status_mask) in vi_set_vce_clocks()
1187 orig = data = RREG32_SMC(ixTHM_CLK_CNTL); in vi_program_aspm()
1420 pc = RREG32_SMC(ixSMC_PC_C); in vi_need_reset_on_init()
[all …]
H A Dvce_v3_0.c373 tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) & in vce_v3_0_get_harvest_config()
377 tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) & in vce_v3_0_get_harvest_config()
839 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); in vce_v3_0_get_clockgating_state()
841 data = RREG32_SMC(ixCURRENT_PG_STATUS); in vce_v3_0_get_clockgating_state()
H A Duvd_v4_2.c733 if (!(RREG32_SMC(ixCURRENT_PG_STATUS) & in uvd_v4_2_set_powergating_state()
744 if (RREG32_SMC(ixCURRENT_PG_STATUS) & in uvd_v4_2_set_powergating_state()
H A Duvd_v6_0.c363 (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK)) in uvd_v6_0_early_init()
1509 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); in uvd_v6_0_get_clockgating_state()
1511 data = RREG32_SMC(ixCURRENT_PG_STATUS); in uvd_v6_0_get_clockgating_state()
H A Damdgpu_cgs.c66 return RREG32_SMC(index); in amdgpu_cgs_read_ind_register()
H A Duvd_v5_0.c847 if (RREG32_SMC(ixCURRENT_PG_STATUS) & in uvd_v5_0_get_clockgating_state()
H A Damdgpu.h1344 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) macro
1375 u32 tmp = RREG32_SMC(_Reg); \
H A Dsi.c1882 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) in si_vce_send_vcepll_ctlreq()
H A Damdgpu_debugfs.c785 value = RREG32_SMC(*pos); in amdgpu_debugfs_regs_smc_read()

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