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Searched refs:PACKET3_SET_CONTEXT_REG_START (Results 1 – 19 of 19) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dsi_enums.h251 #define PACKET3_SET_CONTEXT_REG_START 0x000a000 macro
H A Dvid.h344 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
H A Dcikd.h471 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
H A Dsoc15d.h432 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
H A Dnvd.h517 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 macro
H A Dgfx_v7_0.c2496 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_cp_gfx_start()
2504 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_cp_gfx_start()
3906 buffer[count++] = cpu_to_le32(ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_get_csb_buffer()
3916 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v7_0_get_csb_buffer()
H A Dsid.h1558 #define PACKET3_SET_CONTEXT_REG_START 0x000a000 macro
H A Dgfx_v8_0.c1248 PACKET3_SET_CONTEXT_REG_START); in gfx_v8_0_get_csb_buffer()
1259 PACKET3_SET_CONTEXT_REG_START); in gfx_v8_0_get_csb_buffer()
4187 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v8_0_cp_gfx_start()
4195 amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v8_0_cp_gfx_start()
H A Dgfx_v6_0.c2039 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v6_0_cp_gfx_start()
2884 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in gfx_v6_0_get_csb_buffer()
H A Dgfx_v11_0.c859 PACKET3_SET_CONTEXT_REG_START); in gfx_v11_0_get_csb_buffer()
869 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_get_csb_buffer()
3556 PACKET3_SET_CONTEXT_REG_START); in gfx_v11_0_cp_gfx_start()
3564 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v11_0_cp_gfx_start()
H A Dgfx_v10_0.c4322 PACKET3_SET_CONTEXT_REG_START); in gfx_v10_0_get_csb_buffer()
4332 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v10_0_get_csb_buffer()
6361 PACKET3_SET_CONTEXT_REG_START); in gfx_v10_0_cp_gfx_start()
6369 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START; in gfx_v10_0_cp_gfx_start()
H A Dgfx_v9_0.c1649 PACKET3_SET_CONTEXT_REG_START); in gfx_v9_0_get_csb_buffer()
3335 ext->reg_index - PACKET3_SET_CONTEXT_REG_START); in gfx_v9_0_cp_gfx_start()
/linux-6.15/drivers/gpu/drm/radeon/
H A Devergreen_cs.c2319 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START; in evergreen_packet3_check()
2321 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) || in evergreen_packet3_check()
2630 allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START; in evergreen_packet3_check()
3505 allowed_reg_base -= PACKET3_SET_CONTEXT_REG_START; in evergreen_vm_packet3_check()
H A Dnid.h1273 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
H A Dsid.h1786 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
H A Dcikd.h1929 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
H A Devergreend.h1669 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 macro
H A Dsi.c5728 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in si_get_csb_buffer()
H A Dcik.c6732 buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); in cik_get_csb_buffer()