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Searched refs:PACKET3_PREAMBLE_END_CLEAR_STATE (Results 1 – 20 of 20) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dsi_enums.h242 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Dvid.h270 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Dcikd.h397 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Dsoc15d.h345 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Dnvd.h396 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Dsid.h1549 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Dgfx_v6_0.c2047 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v6_0_cp_gfx_start()
2888 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v6_0_get_csb_buffer()
H A Dgfx_v7_0.c2509 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v7_0_cp_gfx_start()
3942 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v7_0_get_csb_buffer()
H A Dgfx_v8_0.c1264 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v8_0_get_csb_buffer()
4200 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
H A Dgfx_v11_0.c875 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v11_0_get_csb_buffer()
3570 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v11_0_cp_gfx_start()
H A Dgfx_v9_0.c1659 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v9_0_get_csb_buffer()
3343 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v9_0_cp_gfx_start()
H A Dgfx_v10_0.c4338 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v10_0_get_csb_buffer()
6375 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v10_0_cp_gfx_start()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dnid.h1263 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Dsid.h1777 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Dcikd.h1855 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Devergreend.h1658 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
H A Dni.c1559 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cayman_cp_start()
H A Dsi.c3579 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in si_cp_start()
5749 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in si_get_csb_buffer()
H A Dcik.c4007 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_cp_gfx_start()
6758 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_get_csb_buffer()
H A Devergreen.c3033 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in evergreen_cp_start()