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Searched refs:PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (Results 1 – 20 of 20) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dsi_enums.h241 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dvid.h269 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dcikd.h396 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dsoc15d.h344 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dnvd.h395 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dsid.h1548 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dgfx_v6_0.c2032 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v6_0_cp_gfx_start()
2864 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v6_0_get_csb_buffer()
H A Dgfx_v7_0.c2485 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v7_0_cp_gfx_start()
3895 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v7_0_get_csb_buffer()
H A Dgfx_v8_0.c1236 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_get_csb_buffer()
4174 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
H A Dgfx_v11_0.c847 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v11_0_get_csb_buffer()
3543 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v11_0_cp_gfx_start()
H A Dgfx_v9_0.c1637 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v9_0_get_csb_buffer()
3322 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v9_0_cp_gfx_start()
H A Dgfx_v10_0.c4310 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v10_0_get_csb_buffer()
6348 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in gfx_v10_0_cp_gfx_start()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dnid.h1262 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dsid.h1776 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dcikd.h1854 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Devergreend.h1657 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) macro
H A Dni.c1553 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cayman_cp_start()
H A Dsi.c3573 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in si_cp_start()
5707 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in si_get_csb_buffer()
H A Dcik.c3997 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_cp_gfx_start()
6711 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_get_csb_buffer()
H A Devergreen.c3027 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in evergreen_cp_start()