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Searched refs:PACKET3 (Results 1 – 25 of 34) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c2216 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v7_0_ring_emit_ib_gfx()
2218 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v7_0_ring_emit_ib_gfx()
2310 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); in gfx_v7_0_ring_test_ib()
2478 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v7_0_cp_gfx_start()
3181 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_wreg()
4011 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch()
4019 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch()
4027 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch()
4035 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v7_0_ring_emit_gds_switch()
5019 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
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H A Dgfx_v6_0.c1813 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in gfx_v6_0_ring_emit_vgt_flush()
1827 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in gfx_v6_0_ring_emit_fence()
1861 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v6_0_ring_emit_ib()
1863 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v6_0_ring_emit_ib()
1901 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); in gfx_v6_0_ring_test_ib()
2017 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v6_0_cp_gfx_start()
2038 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count)); in gfx_v6_0_cp_gfx_start()
2049 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in gfx_v6_0_cp_gfx_start()
2285 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v6_0_ring_emit_pipeline_sync()
2312 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v6_0_ring_emit_vm_flush()
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H A Dgfx_v8_0.c891 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v8_0_ring_test_ib()
1562 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds()
1588 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds()
1614 ib.ptr[ib.length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v8_0_do_edc_gpr_workarounds()
4184 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v8_0_cp_gfx_start()
4206 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v8_0_cp_gfx_start()
6073 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v8_0_ring_emit_ib_gfx()
6075 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v8_0_ring_emit_ib_gfx()
6938 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6985 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
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H A Dgfx_v9_0.c1136 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_0_write_data_to_reg()
1220 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v9_0_ring_test_ib()
3332 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v9_0_cp_gfx_start()
3348 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v9_0_cp_gfx_start()
4570 amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in gfx_v9_0_do_edc_gds_workarounds()
5394 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in gfx_v9_0_ring_emit_ib_gfx()
5396 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v9_0_ring_emit_ib_gfx()
7457 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
7514 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
7574 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
[all …]
H A Dsi_enums.h156 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
159 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Dgfx_v11_0.c480 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v11_0_write_data_to_reg()
493 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v11_0_wait_reg_mem()
612 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v11_0_ring_test_ib()
3553 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v11_0_cp_gfx_start()
5679 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v11_0_ring_emit_ib_gfx()
5878 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); in gfx_v11_0_ring_emit_init_cond_exec()
5913 amdgpu_ring_write(ring, PACKET3(PACKET3_NOP, 1)); in gfx_v11_0_ring_emit_gfx_shadow()
6096 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); in gfx_v11_0_ring_emit_rreg()
6843 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6899 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
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H A Dvid.h105 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
109 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Dcikd.h232 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
236 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Dgfx_v9_4_3.c202 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v9_4_3_kiq_map_queues()
374 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_4_3_write_data_to_reg()
394 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_4_3_wait_reg_mem()
469 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v9_4_3_ring_test_ib()
2844 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); in gfx_v9_4_3_ring_emit_fence()
2926 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_4_3_ring_emit_fence_kiq()
2935 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_4_3_ring_emit_fence_kiq()
2951 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); in gfx_v9_4_3_ring_emit_rreg()
2981 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v9_4_3_ring_emit_wreg()
4661 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
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H A Dgfx_v12_0.c299 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in gfx_v12_0_kiq_map_queues()
402 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v12_0_wait_reg_mem()
507 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v12_0_ring_test_ib()
4316 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v12_0_ring_emit_ib_gfx()
4437 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v12_0_ring_emit_fence_kiq()
4480 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); in gfx_v12_0_ring_emit_init_cond_exec()
4557 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); in gfx_v12_0_ring_emit_rreg()
4586 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v12_0_ring_emit_wreg()
5256 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
5306 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
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H A Dsoc15d.h50 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
54 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Dgfx_v10_0.c3974 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in gfx_v10_0_write_data_to_reg()
4068 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); in gfx_v10_0_ring_test_ib()
6358 PACKET3(PACKET3_SET_CONTEXT_REG, in gfx_v10_0_cp_gfx_start()
6380 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in gfx_v10_0_cp_gfx_start()
8614 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2); in gfx_v10_0_ring_emit_ib_gfx()
8616 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in gfx_v10_0_ring_emit_ib_gfx()
8817 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); in gfx_v10_0_ring_emit_init_cond_exec()
8956 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4)); in gfx_v10_0_ring_emit_rreg()
9794 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9853 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
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H A Dnvd.h48 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
52 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Dgfx_v9_4_2.c381 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 1); in gfx_v9_4_2_run_shader()
389 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 2); in gfx_v9_4_2_run_shader()
396 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_SET_SH_REG, 3); in gfx_v9_4_2_run_shader()
404 ib->ptr[ib->length_dw++] = PACKET3(PACKET3_DISPATCH_DIRECT, 3); in gfx_v9_4_2_run_shader()
H A Dsid.h1367 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
1371 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Damdgpu_amdkfd_gfx_v10_3.c302 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); in hiq_mqd_load_v10_3()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dni.c1385 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_fence_ring_emit()
1391 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cayman_fence_ring_emit()
1407 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in cayman_ring_ib_execute()
1412 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in cayman_ring_ib_execute()
1428 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_ring_ib_execute()
1534 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in cayman_cp_start()
1552 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1558 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1562 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cayman_cp_start()
2678 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cayman_vm_flush()
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H A Dsi.c3360 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in si_fence_ring_emit()
3391 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in si_ring_ib_execute()
3402 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_ring_ib_execute()
3409 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in si_ring_ib_execute()
3557 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in si_cp_start()
3582 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in si_cp_start()
5060 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_vm_flush()
5075 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_vm_flush()
5083 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in si_vm_flush()
5091 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in si_vm_flush()
[all …]
H A Dcik.c3680 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in cik_copy_cpdma()
3730 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2); in cik_ring_ib_execute()
3748 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2); in cik_ring_ib_execute()
3789 ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); in cik_ib_test()
3990 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in cik_cp_gfx_start()
5682 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
5696 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
5703 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); in cik_vm_flush()
5714 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
8390 nop = PACKET3(PACKET3_NOP, 0x3FFF); in cik_startup()
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H A Dr600.c2697 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in r600_cp_start()
2842 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_ring_test()
2880 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2894 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in r600_fence_ring_emit()
2899 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); in r600_fence_ring_emit()
2937 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in r600_semaphore_ring_emit()
2944 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in r600_semaphore_ring_emit()
2991 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in r600_copy_cpdma()
3002 radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4)); in r600_copy_cpdma()
3379 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); in r600_ring_ib_execute()
[all …]
H A Dr300d.h64 #define PACKET3(op, n) (CP_PACKET3 | \ macro
H A Devergreen.c2935 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in evergreen_ring_ib_execute()
2940 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in evergreen_ring_ib_execute()
2946 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3)); in evergreen_ring_ib_execute()
2953 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in evergreen_ring_ib_execute()
3007 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in evergreen_cp_start()
3026 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start()
3032 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in evergreen_cp_start()
3036 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in evergreen_cp_start()
H A Dsid.h1595 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ macro
1599 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Dcikd.h1691 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ macro
1695 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
H A Drv515d.h204 #define PACKET3(op, n) (CP_PACKET3 | \ macro

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