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Searched refs:N1 (Results 1 – 25 of 55) sorted by relevance

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/linux-6.15/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv40.c63 int N1 = (coef & 0x0000ff00) >> 8; in read_pll_2() local
69 khz = ref * N1 / M1; in read_pll_2()
125 int *N1, int *M1, int *N2, int *M2, int *log2P) in nv40_clk_calc_pll() argument
138 ret = nv04_pll_calc(subdev, &pll, khz, N1, M1, N2, M2, log2P); in nv40_clk_calc_pll()
151 int N1, M1, N2, M2, log2P; in nv40_clk_calc() local
156 &N1, &M1, &N2, &M2, &log2P); in nv40_clk_calc()
162 clk->npll_coef = (N1 << 8) | M1; in nv40_clk_calc()
165 clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_clk_calc()
171 &N1, &M1, NULL, NULL, &log2P); in nv40_clk_calc()
175 clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; in nv40_clk_calc()
H A Dpllnv04.c151 int M1, N1, M2, N2, log2P; in getMNP_double() local
170 for (N1 = minN1; N1 <= maxN1; N1++) { in getMNP_double()
171 calcclk1 = crystal * N1 / M1; in getMNP_double()
211 *pN1 = N1; in getMNP_double()
228 int *N1, int *M1, int *N2, int *M2, int *P) in nv04_pll_calc() argument
233 ret = getMNP_single(subdev, info, freq, N1, M1, P); in nv04_pll_calc()
239 ret = getMNP_double(subdev, info, freq, N1, M1, N2, M2, P); in nv04_pll_calc()
H A Dnv04.c35 int N1, M1, N2, M2, P; in nv04_clk_pll_calc() local
36 int ret = nv04_pll_calc(&clock->subdev, info, clk, &N1, &M1, &N2, &M2, &P); in nv04_clk_pll_calc()
39 pv->N1 = N1; in nv04_clk_pll_calc()
H A Dpll.h9 int *N1, int *M1, int *N2, int *M2, int *P);
H A Dmcp77.c57 int N1, M1; in read_pll() local
70 N1 = (coef & 0x0000ff00) >> 8; in read_pll()
73 clock = ref * N1 / M1; in read_pll()
H A Dnv50.c166 int N1, N2, M1, M2; in read_pll() local
176 N1 = (coef & 0x0000ff00) >> 8; in read_pll()
179 freq = ref * N1 / M1; in read_pll()
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv50.c41 int N1, M1, N2, M2, P; in nv50_devinit_pll_set() local
50 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); in nv50_devinit_pll_set()
60 nvkm_mask(device, info.reg + 4, 0x00ff00ff, (M1 << 16) | N1); in nv50_devinit_pll_set()
69 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1); in nv50_devinit_pll_set()
73 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1); in nv50_devinit_pll_set()
H A Dnv04.c164 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1)) in setPLL_single()
363 int N1, M1, N2, M2, P; in nv04_devinit_pll_set() local
370 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P); in nv04_devinit_pll_set()
375 pv.N1 = N1; in nv04_devinit_pll_set()
/linux-6.15/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dramnv40.c40 int N1, M1, N2, M2; in nv40_ram_calc() local
49 ret = nv04_pll_calc(subdev, &pll, freq, &N1, &M1, &N2, &M2, &log2P); in nv40_ram_calc()
57 ram->coef = (N1 << 8) | M1; in nv40_ram_calc()
60 ram->coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; in nv40_ram_calc()
H A Dramgf100.c143 int N1, M1, P; in gf100_ram_calc() local
216 &N1, NULL, &M1, &P); in gf100_ram_calc()
225 ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1); in gf100_ram_calc()
231 &N1, NULL, &M1, &P); in gf100_ram_calc()
238 ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1); in gf100_ram_calc()
/linux-6.15/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
H A Dpll.h9 uint8_t N1, M1, N2, M2; member
11 uint8_t M1, N1, M2, N2;
/linux-6.15/drivers/dma/dw/
H A DKconfig20 tristate "Renesas RZ/N1 DMAMUX driver"
24 Support the Renesas RZ/N1 DMAMUX which is located in front of
/linux-6.15/drivers/net/pcs/
H A DKconfig29 tristate "Renesas RZ/N1 MII converter"
33 on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in
/linux-6.15/Documentation/arch/arm64/
H A Dsilicon-errata.rst173 | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
175 | ARM | Neoverse-N1 | #1349291 | N/A |
177 | ARM | Neoverse-N1 | #1490853 | N/A |
179 | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 |
181 | ARM | Neoverse-N1 | #3324349 | ARM64_ERRATUM_3194386 |
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Damlogic,axg-audio-clkc.yaml39 - description: input plls to generate clock signals N1
47 - description: slave bit clock N1 provided by external components
57 - description: slave sample clock N1 provided by external components
/linux-6.15/Documentation/devicetree/bindings/net/dsa/
H A Drenesas,rzn1-a5psw.yaml7 title: Renesas RZ/N1 Advanced 5 ports ethernet switch
13 The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and
/linux-6.15/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxl-s905d-phicomm-n1.dts12 model = "Phicomm N1";
/linux-6.15/Documentation/devicetree/bindings/net/pcs/
H A Drenesas,rzn1-miic.yaml7 title: Renesas RZ/N1 MII converter
13 This MII converter is present on the Renesas RZ/N1 SoC family. It is
/linux-6.15/Documentation/devicetree/bindings/pinctrl/
H A Drenesas,rzn1-pinctrl.yaml7 title: Renesas RZ/N1 Pin Controller
19 - const: renesas,rzn1-pinctrl # Generic RZ/N1
/linux-6.15/Documentation/devicetree/bindings/dma/
H A Drenesas,rzn1-dmamux.yaml7 title: Renesas RZ/N1 DMA mux
/linux-6.15/Documentation/devicetree/bindings/rtc/
H A Drenesas,rzn1-rtc.yaml7 title: Renesas RZ/N1 SoCs Real-Time Clock
/linux-6.15/Documentation/ABI/testing/
H A Dsysfs-bus-iio-dac-ad576631 select N0 source, write "1" to select N1 source.
/linux-6.15/Documentation/devicetree/bindings/usb/
H A Drenesas,rzn1-usbf.yaml7 title: Renesas RZ/N1 SoCs USBF (USB Function) controller
/linux-6.15/drivers/net/dsa/
H A DKconfig94 tristate "Renesas RZ/N1 A5PSW Ethernet switch support"
100 RZ/N1 SoC.
/linux-6.15/Documentation/devicetree/bindings/spi/
H A Dsnps,dw-apb-ssi.yaml84 - description: Renesas RZ/N1 SPI Controller
89 - const: renesas,rzn1-spi # RZ/N1

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