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Searched refs:MP1_HWIP (Results 1 – 25 of 34) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c103 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 9)) || in smu_v11_0_init_microcode()
104 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7)))) in smu_v11_0_init_microcode()
213 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_v11_0_check_fw_version()
247 amdgpu_ip_version(adev, MP1_HWIP, 0)); in smu_v11_0_check_fw_version()
475 u32 ip_version = amdgpu_ip_version(adev, MP1_HWIP, 0); in smu_v11_0_init_power()
735 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) || in smu_v11_0_init_display_count()
736 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2) || in smu_v11_0_init_display_count()
738 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13)) in smu_v11_0_init_display_count()
1107 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_v11_0_gfx_off_control()
1606 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_v11_0_baco_set_state()
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H A Dsienna_cichlid_ppt.c78 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == \
98 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13)) in get_table_size()
316 (amdgpu_ip_version(adev, MP1_HWIP, 0) > IP_VERSION(11, 0, 7)) && in sienna_cichlid_get_allowed_feature_mask()
748 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) { in sienna_cichlid_get_smu_metrics_data()
1398 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == in sienna_cichlid_print_clk_levels()
1508 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in sienna_cichlid_populate_umd_state_clk()
2001 if (amdgpu_ip_version(adev, MP1_HWIP, 0) != in sienna_cichlid_read_sensor()
2011 if (amdgpu_ip_version(adev, MP1_HWIP, 0) != in sienna_cichlid_read_sensor()
2436 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == in sienna_cichlid_od_edit_dpm_table()
2703 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) { in sienna_cichlid_get_gpu_metrics()
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H A Dnavi10_ppt.c912 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in navi1x_get_smu_metrics_data()
922 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == in navi1x_get_smu_metrics_data()
925 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == in navi1x_get_smu_metrics_data()
1725 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in navi10_populate_umd_state_clk()
2820 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 5)) in navi10_need_umc_cdr_workaround()
2943 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == in navi10_run_umc_cdr_workaround()
2950 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == in navi10_run_umc_cdr_workaround()
3411 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in navi1x_get_gpu_metrics()
3421 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == in navi1x_get_gpu_metrics()
3424 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == in navi1x_get_gpu_metrics()
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/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dsoc15.c349 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 0) || in soc15_get_xclk()
350 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(12, 0, 1) || in soc15_get_xclk()
351 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) || in soc15_get_xclk()
352 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) || in soc15_get_xclk()
353 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 14)) in soc15_get_xclk()
355 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 0) || in soc15_get_xclk()
356 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(10, 0, 1)) in soc15_get_xclk()
550 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc15_asic_reset_method()
651 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc15_supports_baco()
H A Daldebaran.c38 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) && in aldebaran_is_mode2_default()
150 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2) && in aldebaran_mode2_perform_reset()
325 if (amdgpu_ip_version(reset_context->reset_req_dev, MP1_HWIP, 0) == in aldebaran_mode2_restore_hwcontext()
H A Damdgpu_reset.c183 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in amdgpu_reset_init()
207 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in amdgpu_reset_fini()
H A Ddimgrey_cavefish_reg_init.c41 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
H A Daldebaran_reg_init.c40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in aldebaran_reg_base_init()
H A Darct_reg_init.c40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in arct_reg_base_init()
H A Dvega10_reg_init.c40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega10_reg_base_init()
H A Damdgpu_discovery.c225 [MP1_HWIP] = MP1_HWID,
2107 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in amdgpu_discovery_set_smu_ip_blocks()
2159 amdgpu_ip_version(adev, MP1_HWIP, 0)); in amdgpu_discovery_set_smu_ip_blocks()
2597 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2619 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2642 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); in amdgpu_discovery_set_ip_blocks()
2659 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); in amdgpu_discovery_set_ip_blocks()
2682 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); in amdgpu_discovery_set_ip_blocks()
2712 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); in amdgpu_discovery_set_ip_blocks()
2737 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); in amdgpu_discovery_set_ip_blocks()
H A Dvega20_reg_init.c40 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i])); in vega20_reg_base_init()
H A Dsienna_cichlid.c39 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7) && in sienna_cichlid_is_mode2_default()
H A Damdgpu_fru_eeprom.c62 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in is_fru_eeprom_supported()
H A Damdgpu_ucode.c1229 } else if (block_type == MP1_HWIP) { in amdgpu_ucode_legacy_naming()
1230 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in amdgpu_ucode_legacy_naming()
1410 case MP1_HWIP: in amdgpu_ucode_ip_version_decode()
H A Damdgpu_dev_coredump.c53 [MP1_HWIP] = "MP1",
H A Dsoc24.c204 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in soc24_asic_reset_method()
H A Damdgpu_ras_eeprom.c156 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in __is_ras_eeprom_supported()
196 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in __get_eeprom_i2c_addr()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dyellow_carp_ppt.c1014 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1016 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1017 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
1021 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1023 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1024 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
1028 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1030 if ((amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1031 (amdgpu_ip_version(adev, MP1_HWIP, 0)) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
H A Dsmu_v13_0.c105 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); in smu_v13_0_init_microcode()
198 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 7)) || in smu_v13_0_init_pptable_microcode()
199 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0)) || in smu_v13_0_init_pptable_microcode()
200 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10))) in smu_v13_0_init_pptable_microcode()
236 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_v13_0_check_fw_status()
804 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_v13_0_gfx_off_control()
1784 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2)) { in smu_v13_0_set_performance_level()
1972 if ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 2)) && (!ret && value)) in smu_v13_0_get_dpm_level_count()
2032 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) != IP_VERSION(13, 0, 2)) { in smu_v13_0_set_single_dpm_table()
H A Dsmu_v13_0_0_ppt.c2657 ((amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 0) && in smu_v13_0_0_set_power_profile_mode()
2660 (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) && in smu_v13_0_0_set_power_profile_mode()
2938 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_v13_0_0_mode1_reset()
2971 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)) in smu_v13_0_0_mode2_reset()
2983 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)) in smu_v13_0_0_enable_gfx_features()
3042 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10)) && in smu_v13_0_0_check_ecc_table_support()
3094 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_v13_0_0_wbrf_support_check()
3248 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == in smu_v13_0_0_set_ppt_funcs()
H A Dsmu_v13_0_6_ppt.c279 else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == in smu_v13_0_6_get_metrics_version()
414 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) { in smu_v13_0_x_init_caps()
450 (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12))) in smu_v13_0_6_init_microcode()
459 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, in smu_v13_0_6_init_microcode()
741 amdgpu_ip_version(smu->adev, MP1_HWIP, 0); in smu_v13_0_6_get_pm_metrics()
2205 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) in smu_v13_0_6_is_dpm_running()
3604 smu->message_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ? in smu_v13_0_6_set_ppt_funcs()
3607 smu->feature_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ? in smu_v13_0_6_set_ppt_funcs()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_0_ppt.c733 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) in smu_v14_0_common_get_dpm_freq_by_index()
1013 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) in smu_v14_0_common_get_dpm_ultimate_freq()
1124 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) in smu_v14_0_common_get_dpm_level_count()
1303 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 4)) in smu_v14_0_common_get_dpm_profile_freq()
1313 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 4)) in smu_v14_0_common_get_dpm_profile_freq()
1321 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 4)) in smu_v14_0_common_get_dpm_profile_freq()
1520 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) in smu_v14_0_common_set_fine_grain_gfx_freq_parameters()
1584 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) in smu_v14_0_common_get_dpm_table()
1637 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) in smu_v14_0_common_set_mall_enable()
H A Dsmu_v14_0.c81 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); in smu_v14_0_init_microcode()
176 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 2)) || in smu_v14_0_init_pptable_microcode()
177 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 3))) in smu_v14_0_init_pptable_microcode()
245 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_v14_0_check_fw_version()
260 amdgpu_ip_version(adev, MP1_HWIP, 0)); in smu_v14_0_check_fw_version()
767 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_v14_0_gfx_off_control()
1607 else if (i == 1 && amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) in smu_v14_0_set_jpeg_enable()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/
H A Damdgpu_smu.c560 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && in is_support_sw_smu()
680 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_set_funcs()
875 if ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 1)) || in smu_late_init()
876 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 3))) in smu_late_init()
1569 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_smc_hw_setup()
1786 if (amdgpu_ip_version(adev, MP1_HWIP, 0) < IP_VERSION(11, 0, 0)) { in smu_start_smc_engine()
1897 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_disable_dpms()
1920 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_disable_dpms()
1941 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { in smu_disable_dpms()
2030 (!amdgpu_in_reset(adev)) && amdgpu_ip_version(adev, MP1_HWIP, 0) == in smu_reset_mp1_state()
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