Home
last modified time | relevance | path

Searched refs:MP0_HWIP (Results 1 – 21 of 21) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dpsp_v13_0.c96 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_v13_0_init_microcode()
182 ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || in psp_v13_0_wait_for_bootloader()
183 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || in psp_v13_0_wait_for_bootloader()
184 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ? in psp_v13_0_wait_for_bootloader()
209 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || in psp_v13_0_wait_for_bootloader_steady_state()
210 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) || in psp_v13_0_wait_for_bootloader_steady_state()
211 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) { in psp_v13_0_wait_for_bootloader_steady_state()
780 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) { in psp_v13_0_fatal_error_recovery_quirk()
810 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || in psp_v13_0_get_ras_capability()
828 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) in psp_v13_0_is_aux_sos_load_required()
[all …]
H A Damdgpu_fw_attestation.c125 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(14, 0, 2) || in amdgpu_is_fw_attestation_supported()
126 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(14, 0, 3)) in amdgpu_is_fw_attestation_supported()
H A Damdgpu_psp.c104 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_check_pmfw_centralized_cstate_management()
132 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_init_sriov_microcode()
173 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_early_init()
1402 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= in psp_xgmi_peer_link_info_supported()
1518 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == in psp_xgmi_get_topology_info()
1520 amdgpu_ip_version(psp->adev, MP0_HWIP, 0) == in psp_xgmi_get_topology_info()
2917 (amdgpu_ip_version(adev, MP0_HWIP, 0) == in psp_load_non_psp_fw()
2919 amdgpu_ip_version(adev, MP0_HWIP, 0) == in psp_load_non_psp_fw()
2921 amdgpu_ip_version(adev, MP0_HWIP, 0) == in psp_load_non_psp_fw()
3629 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == in is_ta_fw_applicable()
[all …]
H A Dpsp_v13_0_4.c41 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); in psp_v13_0_4_init_microcode()
43 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_v13_0_4_init_microcode()
H A Ddimgrey_cavefish_reg_init.c40 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
H A Daldebaran_reg_init.c39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in aldebaran_reg_base_init()
H A Darct_reg_init.c39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in arct_reg_base_init()
H A Dpsp_v10_0.c54 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); in psp_v10_0_init_microcode()
H A Damdgpu_ras.c1616 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 2) && in amdgpu_ras_query_error_count_helper()
1617 amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(11, 0, 4)) { in amdgpu_ras_query_error_count_helper()
2021 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in amdgpu_ras_aca_is_supported()
2482 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != in amdgpu_ras_log_on_err_counter()
2484 amdgpu_ip_version(adev, MP0_HWIP, 0) != in amdgpu_ras_log_on_err_counter()
2486 amdgpu_ip_version(adev, MP0_HWIP, 0) != in amdgpu_ras_log_on_err_counter()
3614 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in amdgpu_ras_asic_supported()
3626 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in amdgpu_ras_asic_supported()
3797 (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) || in amdgpu_ras_check_supported()
3799 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)); in amdgpu_ras_check_supported()
[all …]
H A Dvega10_reg_init.c39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega10_reg_base_init()
H A Damdgpu_discovery.c224 [MP0_HWIP] = MP0_HWID,
2043 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in amdgpu_discovery_set_psp_ip_blocks()
2099 amdgpu_ip_version(adev, MP0_HWIP, 0)); in amdgpu_discovery_set_psp_ip_blocks()
2596 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2618 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2641 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); in amdgpu_discovery_set_ip_blocks()
2658 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); in amdgpu_discovery_set_ip_blocks()
2681 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); in amdgpu_discovery_set_ip_blocks()
2711 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); in amdgpu_discovery_set_ip_blocks()
2736 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); in amdgpu_discovery_set_ip_blocks()
H A Dvega20_reg_init.c39 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i])); in vega20_reg_base_init()
H A Dpsp_v11_0.c96 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); in psp_v11_0_init_microcode()
98 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_v11_0_init_microcode()
H A Dpsp_v14_0.c65 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); in psp_v14_0_init_microcode()
67 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in psp_v14_0_init_microcode()
H A Dsoc15.c1477 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 2)) && in soc15_common_get_clockgating_state()
1478 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) && in soc15_common_get_clockgating_state()
1479 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 12)) && in soc15_common_get_clockgating_state()
1480 (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 14))) { in soc15_common_get_clockgating_state()
H A Dpsp_v12_0.c55 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); in psp_v12_0_init_microcode()
H A Dpsp_v3_1.c65 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix)); in psp_v3_1_init_microcode()
H A Damdgpu_ucode.c1177 if (block_type == MP0_HWIP) { in amdgpu_ucode_legacy_naming()
1178 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in amdgpu_ucode_legacy_naming()
1407 case MP0_HWIP: in amdgpu_ucode_ip_version_decode()
H A Damdgpu_dev_coredump.c52 [MP0_HWIP] = "MP0",
H A Damdgpu_virt.c920 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { in amdgpu_virt_fw_load_skip_check()
H A Damdgpu.h716 MP0_HWIP, enumerator