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/linux-6.15/Documentation/arch/powerpc/
H A Dkvm-nested.rst17 and controlled by L1 acting as a hypervisor.
31 The L1 code was added::
45 -> L1 exit).
75 (normally at L1 boot time).
85 - L1 deletes L2 with H_GUEST_DELETE()
96 All these HCALLs are made by the L1 to the L0.
123 L1 to negotiate an agreed set of capabilities::
165 L1::
221 dataBuffer: A L1 real address of the GSB.
608 L1 Implementation details: Caching state
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/linux-6.15/Documentation/virt/kvm/x86/
H A Drunning-nested-guests.rst19 | L1 (Guest Hypervisor) |
33 - L1 – level-1 guest; a VM running on L0; also called the "guest
36 - L2 – level-2 guest; a VM running on L1, this is the "nested guest"
148 able to start an L1 guest with::
191 On AMD systems, once an L1 guest has started an L2 guest, the L1 guest
238 - Kernel, libvirt and QEMU version from L1
248 - ``cat /sys/cpuinfo`` from L1
252 - ``lscpu`` from L1
256 - Full ``dmesg`` output from L1
266 - Output of: ``x86info -a`` from L1
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/linux-6.15/arch/arc/kernel/
H A Dentry-compact.S152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
154 ; This is to avoid a potential L1-L2-L1 scenario
155 ; -L1 IRQ taken
156 ; -L2 interrupts L1 (before L1 ISR could run)
160 ; But both L1 and L2 re-enabled, so another L1 can be taken
161 ; while prev L1 is still unserviced
165 ; L2 interrupting L1 implies both L2 and L1 active
167 ; need to check STATUS32_L2 to determine if L1 was active
320 ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
343 ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier
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/linux-6.15/arch/arm/mm/
H A Dproc-xsc3.S69 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
200 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
201 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
233 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
238 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
280 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
282 mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line
283 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
300 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
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/linux-6.15/arch/powerpc/perf/
H A Dpower8-pmu.c133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
136 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
137 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
138 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
139 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
140 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
H A Dpower9-pmu.c177 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
178 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
179 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
180 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
181 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
182 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
183 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
H A Dpower10-pmu.c133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
135 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_LD_PREFETCH_CACHE_LINE_MISS);
136 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
137 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
138 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
139 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ);
/linux-6.15/security/apparmor/include/
H A Dperms.h186 #define xcheck_ns_labels(L1, L2, FN, args...) \ argument
189 fn_for_each((L1), __p1, FN(__p1, (L2), args)); \
193 #define xcheck_labels_profiles(L1, L2, FN, args...) \ argument
194 xcheck_ns_labels((L1), (L2), xcheck_ns_profile_label, (FN), args)
196 #define xcheck_labels(L1, L2, P, FN1, FN2) \ argument
197 xcheck(fn_for_each((L1), (P), (FN1)), fn_for_each((L2), (P), (FN2)))
H A Dlabel.h219 #define fn_for_each2_XXX(L1, L2, P, FN, ...) \ argument
223 label_for_each ## __VA_ARGS__(i, (L1), (L2), (P)) { \
229 #define fn_for_each_in_merge(L1, L2, P, FN) \ argument
230 fn_for_each2_XXX((L1), (L2), P, FN, _in_merge)
231 #define fn_for_each_not_in_set(L1, L2, P, FN) \ argument
232 fn_for_each2_XXX((L1), (L2), P, FN, _not_in_set)
/linux-6.15/arch/hexagon/lib/
H A Dmemset.S159 if (r2==#0) jump:nt .L1
186 if (p1) jump .L1
197 if (p0.new) jump:nt .L1
208 if (p0.new) jump:nt .L1
284 .L1: label
/linux-6.15/Documentation/locking/
H A Dlockdep-design.rst145 <L1> -> <L2>
146 <L2> -> <L1>
521 L1 -> L2
608 L1 -> L2 ... -> Ln -> L1
612 L1 -> L2
616 Ln -> L1
620 Firstly let's make one CPU/task get the L1 in L1 -> L2, and then another get
624 And then because we have L1 -> L2, so the holder of L1 is going to acquire L2
625 in L1 -> L2, however since L2 is already held by another CPU/task, plus L1 ->
645 for L1 and holding Ln, so we will have Ln -> L1 in the dependency graph. Similarly,
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H A Drt-mutex-design.rst47 grab lock L1 (owned by C)
139 Mutexes: L1, L2, L3, L4
141 A owns: L1
142 B blocked on L1
159 F->L5->B->L1->A
180 G->L2->B->L1->A
236 mutex_lock(L1);
240 mutex_unlock(L1);
245 mutex_lock(L1);
251 mutex_unlock(L1);
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/linux-6.15/Documentation/translations/it_IT/locking/
H A Dlockdep-design.rst22 che un processo cerca di acquisire L2 mentre già trattiene L1. Dal punto di
23 vista di lockdep, i due blocchi (L1 ed L2) non sono per forza correlati: quella
143 <L1> -> <L2>
144 <L2> -> <L1>
531 L1 -> L2
619 L1 -> L2 ... -> Ln -> L1
623 L1 -> L2
627 Ln -> L1
632 Per prima cosa facciamo sì che un processo/processore prenda L1 in L1 -> L2, poi
636 Poi visto che abbiamo L1 -> L2, chi trattiene L1 vorrà acquisire L2 in L1 -> L2,
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/linux-6.15/arch/m68k/fpsp040/
H A Dsetox.S104 | 3.1 R := X + N*L1, where L1 := single-precision(-log2/64).
106 | Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate
108 | b) N*L1 is exact because N is no longer than 22 bits and
109 | L1 is no longer than 24 bits.
111 | Thus, R is practically X+N(L1+L2) to full 64 bits.
505 fmuls #0xBC317218,%fp0 | ...N * L1, L1 = lead(-log2/64)
506 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
507 faddx %fp1,%fp0 | ...X + N*L1
671 fmuls #0xBC317218,%fp0 | ...N * L1, L1 = lead(-log2/64)
672 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
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/linux-6.15/drivers/pci/pcie/
H A DKconfig82 state L0/L0s/L1.
108 Enable PCI Express ASPM L0s and L1 where possible, even if the
115 Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
116 possible. This would result in higher power savings while staying in L1
123 Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
/linux-6.15/arch/m68k/lib/
H A Ddivsi3.S95 jpl L1
102 L1: movel sp@(8), d0 /* d0 = dividend */ label
/linux-6.15/Documentation/devicetree/bindings/media/
H A Dst-rc.txt10 - rx-mode: can be "infrared" or "uhf". This property specifies the L1
13 - tx-mode: should be "infrared". This property specifies the L1
/linux-6.15/arch/alpha/boot/
H A Dbootp.c65 #define L1 ((unsigned long *) 0x200802000) macro
77 pcb_va->ptbr = L1[1] >> 32; in pal_init()
H A Dmain.c59 #define L1 ((unsigned long *) 0x200802000) macro
71 pcb_va->ptbr = L1[1] >> 32; in pal_init()
/linux-6.15/Documentation/translations/zh_CN/arch/arm64/
H A Dmemory.txt90 | | +---------------------> [38:30] L1 索引
105 | +-------------------------------> [47:42] L1 索引
/linux-6.15/arch/riscv/lib/
H A Dtishift.S10 beqz a2, .L1
21 .L1: label
/linux-6.15/Documentation/driver-api/
H A Dedac.rst155 - CPU caches (L1 and L2)
165 For example, a cache could be composed of L1, L2 and L3 levels of cache.
166 Each CPU core would have its own L1 cache, while sharing L2 and maybe L3
174 cpu/cpu0/.. <L1 and L2 block directory>
175 /L1-cache/ce_count
179 cpu/cpu1/.. <L1 and L2 block directory>
180 /L1-cache/ce_count
186 the L1 and L2 directories would be "edac_device_block's"
/linux-6.15/tools/perf/Documentation/
H A Dperf-c2c.txt217 L1Hit - store accesses that hit L1
218 L1Miss - store accesses that missed L1
221 Core Load Hit - FB, L1, L2
222 - count of load hits in FB (Fill Buffer), L1 and L2 cache
243 Store Refs - L1 Hit, L1 Miss, N/A
244 - % of store accesses that hit L1, missed L1 and N/A (no available) memory
/linux-6.15/arch/arm/mach-omap2/
H A Dsram243x.S39 str r3, [r2] @ go to L1-freq operation
42 mov r9, #0x1 @ set up for L1 voltage call
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
105 str r5, [r4] @ Force transition to L1
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
200 str r8, [r10] @ Force transition to L1
H A Dsram242x.S39 str r3, [r2] @ go to L1-freq operation
42 mov r9, #0x1 @ set up for L1 voltage call
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
105 str r5, [r4] @ Force transition to L1
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
200 str r8, [r10] @ Force transition to L1

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