Searched refs:KVM_REG_RISCV_CSR (Results 1 – 4 of 4) sorted by relevance
126 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect): in filter_reg()127 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1): in filter_reg()128 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2): in filter_reg()129 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh): in filter_reg()130 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph): in filter_reg()131 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h): in filter_reg()132 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h): in filter_reg()337 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR); in csr_id_to_str()340 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR); in csr_id_to_str()657 case KVM_REG_RISCV_CSR: in print_reg()[all …]
530 KVM_REG_RISCV_CSR); in kvm_riscv_vcpu_get_reg_csr()572 KVM_REG_RISCV_CSR); in kvm_riscv_vcpu_set_reg_csr()868 u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CSR | in copy_csr_reg_indices()885 u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CSR | in copy_csr_reg_indices()903 u64 reg = KVM_REG_RISCV | size | KVM_REG_RISCV_CSR | in copy_csr_reg_indices()1244 case KVM_REG_RISCV_CSR: in kvm_riscv_vcpu_set_reg()1277 case KVM_REG_RISCV_CSR: in kvm_riscv_vcpu_get_reg()
34 #define RISCV_GENERAL_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \
237 #define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT) macro