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Searched refs:HDMI_ACR_N_44 (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.h185 SE_SF(HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
263 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
457 uint8_t HDMI_ACR_N_44; member
589 uint32_t HDMI_ACR_N_44; member
H A Ddce_stream_encoder.c1308 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); in dce110_se_setup_hdmi_audio()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dio/dcn32/
H A Ddcn32_dio_stream_encoder.h80 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
/linux-6.15/drivers/gpu/drm/amd/display/dc/dio/dcn401/
H A Ddcn401_dio_stream_encoder.h82 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
/linux-6.15/drivers/gpu/drm/amd/display/dc/dio/dcn10/
H A Ddcn10_stream_encoder.h255 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
471 type HDMI_ACR_N_44;\
H A Ddcn10_stream_encoder.c1294 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); in enc1_se_setup_hdmi_audio()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dio/dcn314/
H A Ddcn314_dio_stream_encoder.h159 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
/linux-6.15/drivers/gpu/drm/amd/display/dc/dio/dcn35/
H A Ddcn35_dio_stream_encoder.h160 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
/linux-6.15/drivers/gpu/drm/amd/display/dc/dio/dcn30/
H A Ddcn30_dio_stream_encoder.h159 SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\
H A Ddcn30_dio_stream_encoder.c800 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); in enc3_se_setup_hdmi_audio()
/linux-6.15/drivers/gpu/drm/radeon/
H A Drv770d.h794 # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) macro
H A Devergreend.h648 # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0) macro
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v6_0.c1504 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); in dce_v6_0_audio_set_acr()
H A Ddce_v10_0.c1502 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); in dce_v10_0_afmt_update_ACR()
H A Ddce_v11_0.c1551 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); in dce_v11_0_afmt_update_ACR()