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Searched refs:GET_INST (Results 1 – 22 of 22) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v1_2.c92 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
95 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
99 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
102 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
106 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
109 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
113 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
116 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_init_gart_aperture_regs()
295 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_disable_identity_aperture()
298 WREG32_SOC15(GC, GET_INST(GC, i), in gfxhub_v1_2_xcc_disable_identity_aperture()
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H A Dgfx_v9_4_3.c348 dev_inst = GET_INST(GC, i); in gfx_v9_4_3_init_golden_registers()
1984 GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_kiq_init_register()
1990 GC, GET_INST(GC, xcc_id), in gfx_v9_4_3_xcc_kiq_init_register()
2290 GET_INST(GC, xcc_id)); in gfx_v9_4_3_xcc_fini()
4353 GET_INST(GC, xcc_id), in gfx_v9_4_3_inst_query_ras_err_count()
4362 GET_INST(GC, xcc_id), in gfx_v9_4_3_inst_query_ras_err_count()
4383 GET_INST(GC, xcc_id), in gfx_v9_4_3_inst_query_ras_err_count()
4419 GET_INST(GC, xcc_id)); in gfx_v9_4_3_inst_reset_ras_err_count()
4424 GET_INST(GC, xcc_id)); in gfx_v9_4_3_inst_reset_ras_err_count()
4441 GET_INST(GC, xcc_id)); in gfx_v9_4_3_inst_reset_ras_err_count()
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H A Damdgpu_amdkfd_gfx_v9.c59 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_unlock_srbm()
171 WREG32_SOC15(GC, GET_INST(GC, inst), mmCPC_INT_CNTL, in kgd_gfx_v9_init_interrupts()
636 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_CMD, sq_cmd); in kgd_gfx_v9_wave_control_execute()
909 *wait_times = RREG32_SOC15_RLC(GC, GET_INST(GC, inst), in kgd_gfx_v9_get_iq_wait_times()
1034 soc15_grbm_select(adev, 1, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_get_cu_occupancy()
1072 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst)); in kgd_gfx_v9_get_cu_occupancy()
1111 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_LO, in kgd_gfx_v9_program_trap_handler_settings()
1113 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_HI, in kgd_gfx_v9_program_trap_handler_settings()
1119 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_LO, in kgd_gfx_v9_program_trap_handler_settings()
1121 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_HI, in kgd_gfx_v9_program_trap_handler_settings()
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H A Damdgpu_jpeg.h39 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
42 JPEG, GET_INST(JPEG, inst_idx), \
66 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
68 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
71 JPEG, GET_INST(JPEG, inst_idx), \
80 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
82 WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx), \
H A Damdgpu_amdkfd_gc_9_4_3.c48 SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id), in get_sdma_rlc_reg_offset()
228 unsigned int phy_inst = GET_INST(GC, xcc_inst); in kgd_gfx_v9_4_3_set_pasid_vmid_mapping()
299 hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_MQD_BASE_ADDR); in kgd_gfx_v9_4_3_hqd_load()
338 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_LO, in kgd_gfx_v9_4_3_hqd_load()
340 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_HI, in kgd_gfx_v9_4_3_hqd_load()
342 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_PQ_WPTR_POLL_ADDR, in kgd_gfx_v9_4_3_hqd_load()
346 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_PQ_WPTR_POLL_CNTL1, in kgd_gfx_v9_4_3_hqd_load()
351 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_EOP_RPTR, in kgd_gfx_v9_4_3_hqd_load()
355 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), regCP_HQD_ACTIVE, data); in kgd_gfx_v9_4_3_hqd_load()
493 WREG32_XCC((SOC15_REG_OFFSET(GC, GET_INST(GC, inst), in kgd_gfx_v9_4_3_set_address_watch()
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H A Djpeg_v5_0_1.c155 jpeg_inst = GET_INST(JPEG, i); in jpeg_v5_0_1_sw_init()
252 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) in jpeg_v5_0_1_hw_init()
256 jpeg_inst = GET_INST(JPEG, i); in jpeg_v5_0_1_hw_init()
344 int jpeg_inst = GET_INST(JPEG, i); in jpeg_v5_0_1_init_inst()
365 int jpeg_inst = GET_INST(JPEG, i); in jpeg_v5_0_1_deinit_inst()
381 int jpeg_inst = GET_INST(JPEG, ring->me); in jpeg_v5_0_1_init_jrbc()
513 WREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, ring->me), in jpeg_v5_0_1_dec_ring_set_wptr()
530 ret &= ((RREG32_SOC15_OFFSET(JPEG, GET_INST(JPEG, i), in jpeg_v5_0_1_is_idle()
550 ret &= SOC15_WAIT_ON_RREG_OFFSET(JPEG, GET_INST(JPEG, i), in jpeg_v5_0_1_wait_for_idle()
669 int jpeg_inst = GET_INST(JPEG, ring->me); in jpeg_v5_0_1_core_stall_reset()
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H A Djpeg_v4_0_3.c161 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_sw_init()
266 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_start_sriov()
387 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_hw_init()
402 VCN, GET_INST(VCN, i), in jpeg_v4_0_3_hw_init()
485 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_disable_clock_gating()
510 jpeg_inst = GET_INST(JPEG, inst_idx); in jpeg_v4_0_3_enable_clock_gating()
532 int jpeg_inst = GET_INST(JPEG, inst); in jpeg_v4_0_3_start_inst()
624 int jpeg_inst = GET_INST(JPEG, inst); in jpeg_v4_0_3_stop_inst()
1192 jpeg_inst = GET_INST(JPEG, i); in jpeg_v4_0_3_set_dec_ring_funcs()
1266 NULL, 0, GET_INST(VCN, jpeg_inst), in jpeg_v4_0_3_inst_query_ras_error_count()
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H A Dvcn_v5_0_1.c115 vcn_inst = GET_INST(VCN, i); in vcn_v5_0_1_sw_init()
207 if (RREG32_SOC15(VCN, GET_INST(VCN, 0), regVCN_RRMT_CNTL) & 0x100) in vcn_v5_0_1_hw_init()
210 vcn_inst = GET_INST(VCN, i); in vcn_v5_0_1_hw_init()
323 vcn_inst = GET_INST(VCN, inst); in vcn_v5_0_1_mc_resume()
520 vcn_inst = GET_INST(VCN, vinst->inst); in vcn_v5_0_1_pause_dpg_mode()
571 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v5_0_1_start_dpg_mode()
687 vcn_inst = GET_INST(VCN, i); in vcn_v5_0_1_start()
830 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v5_0_1_stop_dpg_mode()
863 vcn_inst = GET_INST(VCN, i); in vcn_v5_0_1_stop()
979 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, in vcn_v5_0_1_unified_ring_set_wptr()
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H A Dvcn_v4_0_3.c184 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_sw_init()
325 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_hw_init()
336 VCN, GET_INST(VCN, ring->me), in vcn_v4_0_3_hw_init()
344 VCN, GET_INST(VCN, ring->me), in vcn_v4_0_3_hw_init()
451 vcn_inst = GET_INST(VCN, inst_idx); in vcn_v4_0_3_mc_resume()
1004 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_start_sriov()
1177 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_start()
1377 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_stop()
1611 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_set_unified_ring_funcs()
1847 inst_id = GET_INST(VCN, i); in vcn_v4_0_3_dump_ip_state()
[all …]
H A Damdgpu_vcn.h146 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \
149 VCN, GET_INST(VCN, inst_idx), \
198 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \
201 VCN, GET_INST(VCN, inst_idx), \
H A Dgmc_v9_0.c892 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
894 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
905 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
907 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
920 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
922 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
935 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
937 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst)); in gmc_v9_0_flush_gpu_tlb()
H A Dsdma_v4_4_2.c115 u32 dev_inst = GET_INST(SDMA0, instance); in sdma_v4_4_2_get_reg_offset()
1668 u32 id = GET_INST(SDMA0, ring->me); in sdma_v4_4_2_reset_queue()
2046 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_CLK_CTRL)); in sdma_v4_4_2_get_clockgating_state()
2051 data = RREG32(SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, 0), regSDMA_POWER_CNTL)); in sdma_v4_4_2_get_clockgating_state()
2195 dev_inst = GET_INST(SDMA0, i); in sdma_v4_4_2_set_ring_funcs()
2465 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); in sdma_v4_4_2_inst_query_ras_error_count()
2503 uint32_t sdma_dev_inst = GET_INST(SDMA0, sdma_inst); in sdma_v4_4_2_inst_reset_ras_error_count()
H A Dsoc15_common.h28 #define GET_INST(ip, inst) \ macro
H A Dnbio_v7_9.c82 dev_inst = GET_INST(SDMA0, instance); in nbio_v7_9_sdma_doorbell_range()
H A Damdgpu_jpeg.c495 inst_id = GET_INST(JPEG, i); in amdgpu_jpeg_dump_ip_state()
H A Dgmc_v12_0.c314 1 << vmid, GET_INST(GC, 0)); in gmc_v12_0_flush_gpu_tlb()
H A Dgmc_v11_0.c240 1 << vmid, GET_INST(GC, 0)); in gmc_v11_0_flush_gpu_tlb()
H A Dgmc_v10_0.c279 1 << vmid, GET_INST(GC, 0)); in gmc_v10_0_flush_gpu_tlb()
H A Damdgpu_device.c798 ret = amdgpu_virt_rlcg_reg_rw(adev, reg, 0, rlcg_flag, GET_INST(GC, xcc_id)); in amdgpu_device_xcc_rreg()
929 amdgpu_virt_rlcg_reg_rw(adev, reg, v, rlcg_flag, GET_INST(GC, xcc_id)); in amdgpu_device_xcc_wreg()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_12_ppt.c293 xcc_id = GET_INST(GC, 0); in smu_v13_0_12_get_smu_metrics_data()
385 xcc_id = GET_INST(GC, i); in smu_v13_0_12_get_gpu_metrics()
393 inst = GET_INST(VCN, i); in smu_v13_0_12_get_gpu_metrics()
416 gpu_metrics->gfxclk_lock_status = metrics->GfxLockXCDMak >> GET_INST(GC, 0); in smu_v13_0_12_get_gpu_metrics()
456 inst = GET_INST(VCN, k); in smu_v13_0_12_get_gpu_metrics()
472 inst = GET_INST(GC, k); in smu_v13_0_12_get_gpu_metrics()
H A Dsmu_v13_0_6_ppt.c1153 xcc_id = GET_INST(GC, 0); in smu_v13_0_6_get_smu_metrics_data()
2541 xcc_id = GET_INST(GC, i); in smu_v13_0_6_get_gpu_metrics()
2549 inst = GET_INST(VCN, i); in smu_v13_0_6_get_gpu_metrics()
2576 version) >> GET_INST(GC, 0); in smu_v13_0_6_get_gpu_metrics()
2645 inst = GET_INST(VCN, k); in smu_v13_0_6_get_gpu_metrics()
2663 inst = GET_INST(GC, k); in smu_v13_0_6_get_gpu_metrics()
/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_device.c711 mapped_xcc = GET_INST(GC, xcc); in kfd_setup_interrupt_bitmap()