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Searched refs:AMDGPU_UVD_FIRMWARE_OFFSET (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_uvd.h32 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 macro
38 8) - AMDGPU_UVD_FIRMWARE_OFFSET)
H A Dvcn_v5_0_1.c339 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v5_0_1_mc_resume()
420 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
H A Dvcn_v4_0_3.c472 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_3_mc_resume()
560 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
1044 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_3_start_sriov()
H A Duvd_v3_1.c246 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v3_1_mc_resume()
H A Duvd_v4_2.c580 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v4_2_mc_resume()
H A Duvd_v5_0.c291 offset = AMDGPU_UVD_FIRMWARE_OFFSET; in uvd_v5_0_mc_resume()
H A Dvcn_v5_0_0.c399 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v5_0_0_mc_resume()
478 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
H A Dvcn_v4_0.c482 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_mc_resume()
560 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1408 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_start_sriov()
H A Dvcn_v3_0.c539 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v3_0_mc_resume()
607 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1439 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v3_0_start_sriov()
H A Dvcn_v2_5.c633 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_5_mc_resume()
701 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1461 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_5_sriov_start()
H A Duvd_v7_0.c699 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in uvd_v7_0_mc_resume()
841 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in uvd_v7_0_sriov_start()
H A Dvcn_v4_0_5.c421 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET0, AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v4_0_5_mc_resume()
502 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
H A Dvcn_v1_0.c369 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v1_0_mc_resume_spg_mode()
440 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
H A Dvcn_v2_0.c400 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_0_mc_resume()
470 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
H A Duvd_v6_0.c615 offset = AMDGPU_UVD_FIRMWARE_OFFSET; in uvd_v6_0_mc_resume()