Home
last modified time | relevance | path

Searched refs:timing (Results 1 – 25 of 331) sorted by relevance

12345678910>>...14

/freebsd-14.2/sys/contrib/device-tree/Bindings/mmc/
H A Dsdhci-am654.yaml62 description: Output tap delay for SD/MMC legacy timing
74 description: Output tap delay for SD high speed timing
80 description: Output tap delay for SD UHS SDR12 timing
86 description: Output tap delay for SD UHS SDR25 timing
92 description: Output tap delay for SD UHS SDR50 timing
104 description: Output tap delay for SD UHS DDR50 timing
110 description: Output tap delay for eMMC DDR52 timing
116 description: Output tap delay for eMMC HS200 timing
122 description: Output tap delay for eMMC HS400 timing
162 description: Input tap delay for MMC DDR50 timing
[all …]
H A Dsdhci-sprd.txt33 - sprd,phy-delay-legacy: Delay value for legacy timing.
34 - sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
35 - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
36 - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
37 - sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
38 - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
39 - sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.
40 - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
41 - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
H A Dsamsung,exynos-dw-mshc.yaml51 samsung,dw-mshc-ddr-timing:
63 See also samsung,dw-mshc-hs400-timing property.
65 samsung,dw-mshc-hs400-timing:
77 Valid values for SDR and DDR CIU clock timing::
83 If missing, values from samsung,dw-mshc-ddr-timing property are used.
85 samsung,dw-mshc-sdr-timing:
97 See also samsung,dw-mshc-hs400-timing property.
111 - samsung,dw-mshc-ddr-timing
112 - samsung,dw-mshc-sdr-timing
148 samsung,dw-mshc-sdr-timing = <0 4>;
[all …]
H A Dexynos-dw-mshc.txt32 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
37 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
41 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
44 Notes for the sdr-timing and ddr-timing values:
50 Valid values for SDR and DDR CIU clock timing for Exynos5250:
89 samsung,dw-mshc-sdr-timing = <2 3>;
90 samsung,dw-mshc-ddr-timing = <1 2>;
91 samsung,dw-mshc-hs400-timing = <0 2>;
H A Dcdns,sdhci.yaml40 description: Value of the delay in the input path for SD high-speed timing
46 description: Value of the delay in the input path for legacy timing
52 description: Value of the delay in the input path for SD UHS SDR12 timing
58 description: Value of the delay in the input path for SD UHS SDR25 timing
64 description: Value of the delay in the input path for SD UHS SDR50 timing
70 description: Value of the delay in the input path for SD UHS DDR50 timing
76 description: Value of the delay in the input path for MMC high-speed timing
82 description: Value of the delay in the input path for eMMC high-speed DDR timing
/freebsd-14.2/sys/dev/mmc/
H A Dmmc.c322 enum mmc_bus_timing timing; in mmc_acquire_bus() local
782 switch (timing) { in mmc_set_card_bus_width()
796 switch (timing) { in mmc_set_card_bus_width()
905 switch (timing) { in mmc_set_timing()
924 switch (timing) { in mmc_set_timing()
1458 switch (timing) { in mmc_timing_to_dtr()
1487 switch (timing) { in mmc_timing_to_string()
1526 switch (timing) { in mmc_host_timing()
1567 for (timing = bus_timing_max; timing > bus_timing_normal; timing--) { in mmc_log_card()
2129 for (timing = max_timing - 1; timing >= in mmc_calculate_clock()
[all …]
/freebsd-14.2/sys/contrib/device-tree/Bindings/mips/cavium/
H A Dbootbus.txt32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
34 - cavium,t-ce: A cell specifying the CE timing (in nS).
36 - cavium,t-oe: A cell specifying the OE timing (in nS).
38 - cavium,t-we: A cell specifying the WE timing (in nS).
40 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
42 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
44 - cavium,t-pause: A cell specifying the PAUSE timing (in nS).
46 - cavium,t-wait: A cell specifying the WAIT timing (in nS).
48 - cavium,t-page: A cell specifying the PAGE timing (in nS).
50 - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
/freebsd-14.2/sys/contrib/device-tree/Bindings/clock/
H A Dnvidia,tegra124-car.txt29 - nvidia,ram-code : Should contain the value of RAM_CODE this timing set
32 Each "emc-timings" node should contain a "timing" subnode for every supported
35 Required properties for "timing" nodes :
36 - clock-frequency : Should contain the memory clock rate to which this timing
39 parent of the EMC clock should be running at this timing.
44 timing.
93 timing-12750000 {
99 timing-20400000 {
/freebsd-14.2/sys/contrib/device-tree/Bindings/ata/
H A Dahci-ceva.txt8 - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
9 - ceva,p1-cominit-params: OOB timing value for COMINIT parameter for port 1.
16 - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
17 - ceva,p1-comwake-params: OOB timing value for COMWAKE parameter for port 1.
24 - ceva,p0-burst-params: Burst timing value for COM parameter for port 0.
25 - ceva,p1-burst-params: Burst timing value for COM parameter for port 1.
32 - ceva,p0-retry-params: Retry interval timing value for port 0.
33 - ceva,p1-retry-params: Retry interval timing value for port 1.
/freebsd-14.2/sys/contrib/device-tree/Bindings/media/xilinx/
H A Dxlnx,v-tc.txt4 The Video Timing Controller is a general purpose video timing generator and
13 - clocks: Must contain a clock specifier for the VTC core and timing
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
H A Dxlnx,v-tpg.txt29 - timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG
33 The xlnx,vtc and timing-gpios properties are mandatory when the TPG is
44 timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>;
/freebsd-14.2/sys/contrib/device-tree/Bindings/display/panel/
H A Dpanel-timing.yaml4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
7 title: panel timing
14 There are different ways of describing the timing data of a panel. The
46 This matches the timing diagrams often found in data sheets.
73 description: Horizontal front porch panel timing
85 description: Horizontal back porch timing
97 description: Horizontal sync length panel timing
109 description: Vertical front porch panel timing
121 description: Vertical back porch panel timing
133 description: Vertical sync length panel timing
H A Ddisplay-timings.yaml18 and to specify the timing that is native for the display.
27 The default display timing is the one specified as native-mode.
32 "^timing":
34 $ref: panel-timing.yaml#
42 * Example that specifies panel timing using minimum, typical,
/freebsd-14.2/sys/dev/drm2/
H A Ddrm_edid.c1053 u8 *t = (u8 *)timing; in mode_in_range()
1096 struct detailed_timing *timing) in drm_dmt_modes_for_range() argument
1131 struct detailed_timing *timing) in drm_gtf_modes_for_range() argument
1159 struct detailed_timing *timing) in drm_cvt_modes_for_range() argument
1198 timing); in do_inferred_modes()
1208 timing); in do_inferred_modes()
1216 timing); in do_inferred_modes()
1243 u8 *est = ((u8 *)timing) + 5; in drm_est3_modes()
1376 struct detailed_timing *timing) in drm_cvt_modes() argument
1455 if (timing->pixel_clock) { in do_detailed_mode()
[all …]
/freebsd-14.2/sys/contrib/device-tree/src/arm/
H A Dtegra124-nyan-blaze-emc.dtsi10 timing-12750000 {
17 timing-20400000 {
24 timing-40800000 {
31 timing-68000000 {
38 timing-102000000 {
45 timing-204000000 {
52 timing-300000000 {
59 timing-396000000 {
68 timing-600000000 {
88 timing-12750000 {
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi10 timing-12750000 {
17 timing-20400000 {
24 timing-40800000 {
31 timing-68000000 {
38 timing-102000000 {
45 timing-204000000 {
52 timing-300000000 {
59 timing-396000000 {
66 timing-528000000 {
100 timing-12750000 {
[all …]
H A Dtegra30-asus-tf300t.dts150 timing-25500000 {
160 timing-51000000 {
170 timing-102000000 {
180 timing-204000000 {
190 timing-333500000 {
200 timing-667000000 {
215 timing-25500000 {
225 timing-51000000 {
280 timing-25500000 {
290 timing-51000000 {
[all …]
H A Dtegra124-apalis-emc.dtsi14 timing-12750000 {
21 timing-20400000 {
28 timing-40800000 {
35 timing-68000000 {
42 timing-102000000 {
49 timing-204000000 {
56 timing-300000000 {
63 timing-396000000 {
70 timing-528000000 {
104 timing-12750000 {
[all …]
H A Dtegra30-asus-tf300tg.dts224 timing-25500000 {
234 timing-51000000 {
244 timing-102000000 {
254 timing-204000000 {
264 timing-333500000 {
289 timing-25500000 {
299 timing-51000000 {
354 timing-25500000 {
364 timing-51000000 {
421 timing-25500000 {
[all …]
H A Dtegra30-asus-tf201.dts116 timing-25500000 {
126 timing-51000000 {
136 timing-102000000 {
146 timing-204000000 {
156 timing-400000000 {
171 timing-25500000 {
181 timing-51000000 {
191 timing-102000000 {
201 timing-204000000 {
228 timing-25500000 {
[all …]
H A Dtegra30-asus-tf700t.dts145 timing-25500000 {
155 timing-51000000 {
165 timing-102000000 {
175 timing-204000000 {
185 timing-400000000 {
195 timing-800000000 {
210 timing-25500000 {
220 timing-51000000 {
230 timing-102000000 {
277 timing-25500000 {
[all …]
H A Dexynos5410-smdk5410.dts71 samsung,dw-mshc-sdr-timing = <2 3>;
72 samsung,dw-mshc-ddr-timing = <1 2>;
81 samsung,dw-mshc-sdr-timing = <2 3>;
82 samsung,dw-mshc-ddr-timing = <1 2>;
128 samsung,srom-timing = <9 12 1 9 1 1>;
H A Dexynos5260-xyref5260.dts99 samsung,dw-mshc-sdr-timing = <0 4>;
100 samsung,dw-mshc-ddr-timing = <0 2>;
111 samsung,dw-mshc-sdr-timing = <2 3>;
112 samsung,dw-mshc-ddr-timing = <1 2>;
/freebsd-14.2/sys/dev/ow/
H A Dowll_if.m44 # Maxim datasheets also describe how to use UARTs to generate timing,
47 # Chapter 4 has all the electrical timing diagrams that make up the link
94 struct ow_timing *timing; /* timing values */
112 struct ow_timing *timing; /* timing values */
130 struct ow_timing *timing; /* timing values */
154 struct ow_timing *timing; /* timing values */
/freebsd-14.2/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dintel,ixp4xx-expansion-peripheral-props.yaml19 description: Address timing, extend address phase with n cycles.
24 description: Setup chip select timing, extend setup phase with n cycles.
29 description: Strobe timing, extend strobe phase with n cycles.
34 description: Hold timing, extend hold phase with n cycles.
39 description: Recovery timing, extend recovery phase with n cycles.

12345678910>>...14