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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td14 def: Pat<(int_hexagon_A2_abs IntRegs:$src1),
15 (A2_abs IntRegs:$src1)>, Requires<[HasV5]>;
16 def: Pat<(int_hexagon_A2_absp DoubleRegs:$src1),
18 def: Pat<(int_hexagon_A2_abssat IntRegs:$src1),
62 def: Pat<(int_hexagon_A2_aslh IntRegs:$src1),
64 def: Pat<(int_hexagon_A2_asrh IntRegs:$src1),
110 def: Pat<(int_hexagon_A2_satb IntRegs:$src1),
112 def: Pat<(int_hexagon_A2_sath IntRegs:$src1),
176 def: Pat<(int_hexagon_A2_tfr IntRegs:$src1),
1809 def: Pat<(int_hexagon_V6_hi HvxWR:$src1),
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
13 (MI HvxVR:$src1, IntRegs:$src2)>;
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
26 (MI HvxVR:$src1, HvxVR:$src2)>;
28 (MI HvxVR:$src1, HvxVR:$src2)>;
33 (MI HvxWR:$src1, HvxWR:$src2)>;
35 (MI HvxWR:$src1, HvxWR:$src2)>;
92 def: Pat<(IntID IntRegs:$src1),
93 (MI IntRegs:$src1)>;
[all …]
H A DHexagonIntrinsicsV60.td85 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
87 (MI IntRegs:$src1)>;
91 def: Pat<(IntID HvxVR:$src1),
92 (MI HvxVR:$src1)>;
95 (MI HvxVR:$src1)>;
99 def: Pat<(IntID HvxWR:$src1),
100 (MI HvxWR:$src1)>;
103 (MI HvxWR:$src1)>;
107 def: Pat<(IntID HvxQR:$src1),
108 (MI HvxQR:$src1)>;
[all …]
H A DHexagonIntrinsics.td135 def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2),
136 (C2_tfrpr (C2_cmpgt I32:$src2, I32:$src1))>;
137 def : Pat <(int_hexagon_C2_cmpltu I32:$src1, I32:$src2),
138 (C2_tfrpr (C2_cmpgtu I32:$src2, I32:$src1))>;
289 def: Pat<(IntID HvxVR:$src1, u3_0ImmPred:$src2),
290 (MI HvxVR:$src1, HvxVR:$src1, u3_0ImmPred:$src2)>,
294 (MI HvxVR:$src1, HvxVR:$src1, u3_0ImmPred:$src2)>,
299 def: Pat<(IntID HvxVR:$src1, u3_64_ImmPred:$src2),
300 (MI HvxVR:$src1, HvxVR:$src1,
305 (MI HvxVR:$src1, HvxVR:$src1, (SUB_128_VAL u3_128_ImmPred:$src2))>,
[all …]
/freebsd-14.2/contrib/sendmail/libsm/
H A Dt-strl.c92 (void) sm_strlcpy(src1[k], "abcdef", sizeof src1);
99 one = sm_strlcpyn(dst1, 10, 3, src1[0], "/", src1[1]);
103 one = sm_strlcpyn(dst1, 5, 3, src1[0], "/", src1[1]);
104 two = sm_snprintf(dst2, 5, "%s/%s", src1[0], src1[1]);
107 one = sm_strlcpyn(dst1, 0, 3, src1[0], "/", src1[1]);
111 one = sm_strlcpyn(dst1, sizeof dst1, 5, src1[0], "/", src1[1], "/", src1[2]);
112 two = sm_snprintf(dst2, sizeof dst2, "%s/%s/%s", src1[0], src1[1], src1[2]);
115 one = sm_strlcpyn(dst1, 15, 5, src1[0], "/", src1[1], "/", src1[2]);
116 two = sm_snprintf(dst2, 15, "%s/%s/%s", src1[0], src1[1], src1[2]);
119 one = sm_strlcpyn(dst1, 20, 5, src1[0], "/", src1[1], "/", src1[2]);
[all …]
/freebsd-14.2/contrib/llvm-project/clang/lib/Headers/
H A Damxintrin.h154 __builtin_ia32_tdpbssd((dst), (src0), (src1))
173 __builtin_ia32_tdpbsud((dst), (src0), (src1))
192 __builtin_ia32_tdpbusd((dst), (src0), (src1))
211 __builtin_ia32_tdpbuud((dst), (src0), (src1))
229 __builtin_ia32_tdpbf16ps((dst), (src0), (src1))
370 __tile1024i src1) { in __tile_dpbssd() argument
372 src0.tile, src1.tile); in __tile_dpbssd()
393 __tile1024i src1) { in __tile_dpbsud() argument
395 src0.tile, src1.tile); in __tile_dpbsud()
416 __tile1024i src1) { in __tile_dpbusd() argument
[all …]
H A Damxcomplexintrin.h112 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_cmmimfp16ps_internal() argument
113 return __builtin_ia32_tcmmimfp16ps_internal(m, n, k, dst, src1, src2); in _tile_cmmimfp16ps_internal()
118 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_cmmrlfp16ps_internal() argument
119 return __builtin_ia32_tcmmrlfp16ps_internal(m, n, k, dst, src1, src2); in _tile_cmmrlfp16ps_internal()
140 __tile1024i src1) { in __tile_cmmimfp16ps() argument
141 dst->tile = _tile_cmmimfp16ps_internal(src0.row, src1.col, src0.col, in __tile_cmmimfp16ps()
142 dst->tile, src0.tile, src1.tile); in __tile_cmmimfp16ps()
163 __tile1024i src1) { in __tile_cmmrlfp16ps() argument
164 dst->tile = _tile_cmmrlfp16ps_internal(src0.row, src1.col, src0.col, in __tile_cmmrlfp16ps()
165 dst->tile, src0.tile, src1.tile); in __tile_cmmrlfp16ps()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrXOP.td174 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
181 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
251 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
259 "\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
287 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
295 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
303 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
334 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
343 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
349 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrAMX.td73 def PTILESTOREDV : PseudoI<(outs), (ins GR16:$src1,
100 let Constraints = "$src1 = $dst" in {
150 def PTDPBSSD : PseudoI<(outs), (ins u8imm:$src1,
154 def PTDPBSUD : PseudoI<(outs), (ins u8imm:$src1,
172 let Constraints = "$src1 = $dst" in
202 let Constraints = "$src1 = $dst" in {
205 "tdpfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",
231 let Constraints = "$src1 = $dst" in {
234 "tcmmimfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",
238 "tcmmrlfp16ps\t{$src3, $src2, $src1|$src1, $src2, $src3}",
[all …]
H A DX86InstrKL.td20 def LOADIWKEY : I<0xDC, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
21 "loadiwkey\t{$src2, $src1|$src1, $src2}",
35 let Constraints = "$src1 = $dst",
38 "aesenc128kl\t{$src2, $src1|$src1, $src2}",
40 (X86aesenc128kl VR128:$src1, addr:$src2))]>, T8, XS;
43 "aesdec128kl\t{$src2, $src1|$src1, $src2}",
45 (X86aesdec128kl VR128:$src1, addr:$src2))]>, T8, XS;
48 "aesenc256kl\t{$src2, $src1|$src1, $src2}",
50 (X86aesenc256kl VR128:$src1, addr:$src2))]>, T8, XS;
53 "aesdec256kl\t{$src2, $src1|$src1, $src2}",
[all …]
H A DX86InstrSSE.td52 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5695 "vptest\t{$src2, $src1|$src1, $src2}",
5699 "vptest\t{$src2, $src1|$src1, $src2}",
5705 "vptest\t{$src2, $src1|$src1, $src2}",
5709 "vptest\t{$src2, $src1|$src1, $src2}",
5717 "ptest\t{$src2, $src1|$src1, $src2}",
5721 "ptest\t{$src2, $src1|$src1, $src2}",
6876 "vaesimc\t{$src1, $dst|$dst, $src1}",
6882 "vaesimc\t{$src1, $dst|$dst, $src1}",
6888 "aesimc\t{$src1, $dst|$dst, $src1}",
[all …]
H A DX86InstrFMA.td397 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
404 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
411 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
436 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
442 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
474 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
481 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
488 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
501 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
508 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[all …]
H A DX86InstrCMovSetCC.td17 let Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst",
23 (X86cmov GR16:$src1, GR16:$src2, timm:$cond, EFLAGS))]>,
29 (X86cmov GR32:$src1, GR32:$src2, timm:$cond, EFLAGS))]>,
35 (X86cmov GR64:$src1, GR64:$src2, timm:$cond, EFLAGS))]>, TB;
38 let Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst",
43 [(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
48 [(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
53 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
55 } // Uses = [EFLAGS], Predicates = [HasCMOV], Constraints = "$src1 = $dst"
67 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, timm:$cond, EFLAGS),
[all …]
H A DX86InstrCompiler.td1355 (TEST8rr GR8:$src1, GR8:$src1)>;
1357 (TEST16rr GR16:$src1, GR16:$src1)>;
1359 (TEST32rr GR32:$src1, GR32:$src1)>;
1777 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1778 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1779 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1780 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1783 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr_ND GR8 :$src1, GR8 :$src1)>;
1784 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr_ND GR16:$src1, GR16:$src1)>;
1785 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr_ND GR32:$src1, GR32:$src1)>;
[all …]
H A DX86InstrShiftRotate.td244 def : Pat<(rotl GR8:$src1, (i8 7)), (ROR8r1 GR8:$src1)>;
245 def : Pat<(rotl GR16:$src1, (i8 15)), (ROR16r1 GR16:$src1)>;
246 def : Pat<(rotl GR32:$src1, (i8 31)), (ROR32r1 GR32:$src1)>;
247 def : Pat<(rotl GR64:$src1, (i8 63)), (ROR64r1 GR64:$src1)>;
248 def : Pat<(rotr GR8:$src1, (i8 7)), (ROL8r1 GR8:$src1)>;
249 def : Pat<(rotr GR16:$src1, (i8 15)), (ROL16r1 GR16:$src1)>;
250 def : Pat<(rotr GR32:$src1, (i8 31)), (ROL32r1 GR32:$src1)>;
251 def : Pat<(rotr GR64:$src1, (i8 63)), (ROL64r1 GR64:$src1)>;
254 def : Pat<(rotl GR8:$src1, (i8 7)), (ROR8r1_ND GR8:$src1)>;
255 def : Pat<(rotl GR16:$src1, (i8 15)), (ROR16r1_ND GR16:$src1)>;
[all …]
H A DX86InstrVMX.td19 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
20 "invept\t{$src2, $src1|$src1, $src2}", []>, T8, PD,
22 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
23 "invept\t{$src2, $src1|$src1, $src2}", []>, T8, PD,
25 def INVEPT64_EVEX : I<0xF0, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
26 "invept\t{$src2, $src1|$src1, $src2}", []>,
30 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
31 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8, PD,
33 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
34 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8, PD,
[all …]
H A DX86InstrAVX512.td139 // $src1.
683 "$idx, $src1", "$src1, $idx",
4677 "$src2, $src1", "$src1, $src2",
5724 "$src2, $src1", "$src1, $src2",
5729 "$src2, $src1", "$src1, $src2",
5746 "$src2, $src1", "$src1, $src2",
10422 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
10484 (ins _.RC:$src1), OpcodeStr, "$src1", "$src1",
10489 (ins _.MemOp:$src1), OpcodeStr, "$src1", "$src1",
11085 "$src1", "$src1",
[all …]
H A DX86InstrMisc.td618 "bt{w}\t{$src2, $src1|$src1, $src2}",
622 "bt{l}\t{$src2, $src1|$src1, $src2}",
626 "bt{q}\t{$src2, $src1|$src1, $src2}",
638 "bt{w}\t{$src2, $src1|$src1, $src2}",
641 "bt{l}\t{$src2, $src1|$src1, $src2}",
644 "bt{q}\t{$src2, $src1|$src1, $src2}",
650 "bt{w}\t{$src2, $src1|$src1, $src2}",
654 "bt{l}\t{$src2, $src1|$src1, $src2}",
658 "bt{q}\t{$src2, $src1|$src1, $src2}",
666 "bt{w}\t{$src2, $src1|$src1, $src2}",
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.td208 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
211 // out = (src1 > src0) ? 1 : 0
248 // src1 = Denominator, src2 = Numerator).
273 // src1: dst - rat offset (aka pointer) in dwords
350 SDTCisSameAs<3, 2>, // f32 src1
421 [(int_amdgcn_class node:$src0, node:$src1),
445 [(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),
469 [(int_amdgcn_mul_u24 node:$src0, node:$src1),
470 (AMDGPUmul_u24_impl node:$src0, node:$src1)]>;
473 [(int_amdgcn_mul_i24 node:$src0, node:$src1),
[all …]
/freebsd-14.2/contrib/arm-optimized-routines/string/aarch64/
H A Dmemcmp.S14 #define src1 x0 macro
39 ldp data1, data3, [src1]
68 add src1, src1, 32
99 ldr data1, [src1]
108 ldr data1w, [src1]
116 ldrh data1w, [src1]
141 sub src1, src1, tmp
146 ldr q0, [src1, 16]
149 ldr q2, [src1, 32]
153 ldr q2, [src1, 48]
[all …]
H A Dstrcmp.S20 #define src1 x0 macro
56 sub off2, src2, src1
58 and tmp, src1, 7
66 ldr data2, [src1, off2]
67 ldr data1, [src1], 8
110 bic src1, src1, 7
112 ldr data1, [src1], 8
130 tst src1, 7
147 sub off1, src2, src1
159 ldr data1, [src1], 8
[all …]
/freebsd-14.2/sys/arm64/arm64/
H A Dstrcmp.S22 #define src1 x0 macro
56 sub off2, src2, src1
58 and tmp, src1, 7
66 ldr data2, [src1, off2]
67 ldr data1, [src1], 8
110 bic src1, src1, 7
112 ldr data1, [src1], 8
130 tst src1, 7
147 sub off1, src2, src1
159 ldr data1, [src1], 8
[all …]
H A Dmemcmp.S17 #define src1 x0 macro
36 ldr data1, [src1], 8
44 ldr data1, [src1, limit]
49 ldr data1, [src1], 8
65 and tmp1, src1, 15
67 sub src1, src1, tmp1
75 ldp data1, data1h, [src1], 16
91 add src1, src1, limit
93 ldp data1, data1h, [src1]
118 ldr data1w, [src1], 4
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrCompiler.td25 def mshl_#width : PatFrags<(ops node:$src0, node:$src1),
26 [(shl node:$src0, node:$src1), (shl node:$src0, (shiftMask node:$src1))]>;
28 def msrl_#width : PatFrags<(ops node:$src0, node:$src1),
29 [(srl node:$src0, node:$src1), (srl node:$src0, (shiftMask node:$src1))]>;
31 def msra_#width : PatFrags<(ops node:$src0, node:$src1),
32 [(sra node:$src0, node:$src1), (sra node:$src0, (shiftMask node:$src1))]>;
/freebsd-14.2/contrib/cortex-strings/src/arm/
H A Dstrcmp.S81 #define src1 r0 macro
164 ldrb r2, [src1]
176 orr tmp1, src1, src2
185 eor tmp1, src1, src2
191 and tmp1, src1, #7
192 bic src1, src1, #7
254 ands tmp1, src1, #3
260 ldr data1, [src1], #8
283 bic src1, src1, #3
296 ands tmp1, src1, #3
[all …]

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