Lines Matching refs:src1

208 // out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
211 // out = (src1 > src0) ? 1 : 0
248 //  src1 = Denominator, src2 = Numerator).
253 // Special case divide fixup and flags(src0 = Quotient, src1 =
273 // src1: dst - rat offset (aka pointer) in dwords
350   SDTCisSameAs<3, 2>, // f32 src1
420 def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
421   [(int_amdgcn_class node:$src0, node:$src1),
422    (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
424 def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
425   [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
426    (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
428 def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),
429   [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),
430    (AMDGPUdiv_fixup_impl node:$src0, node:$src1, node:$src2)]>;
444 def AMDGPUpkrtz_f16_f32 : PatFrags<(ops node:$src0, node:$src1),
445   [(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),
446   (AMDGPUpkrtz_f16_f32_impl node:$src0, node:$src1)]>;
448 def AMDGPUpknorm_i16_f32 : PatFrags<(ops node:$src0, node:$src1),
449   [(int_amdgcn_cvt_pknorm_i16 node:$src0, node:$src1),
450   (AMDGPUpknorm_i16_f32_impl node:$src0, node:$src1)]>;
452 def AMDGPUpknorm_u16_f32 : PatFrags<(ops node:$src0, node:$src1),
453   [(int_amdgcn_cvt_pknorm_u16 node:$src0, node:$src1),
454   (AMDGPUpknorm_u16_f32_impl node:$src0, node:$src1)]>;
456 def AMDGPUpk_i16_i32 : PatFrags<(ops node:$src0, node:$src1),
457   [(int_amdgcn_cvt_pk_i16 node:$src0, node:$src1),
458   (AMDGPUpk_i16_i32_impl node:$src0, node:$src1)]>;
460 def AMDGPUpk_u16_u32 : PatFrags<(ops node:$src0, node:$src1),
461   [(int_amdgcn_cvt_pk_u16 node:$src0, node:$src1),
462   (AMDGPUpk_u16_u32_impl node:$src0, node:$src1)]>;
464 def AMDGPUfmad_ftz : PatFrags<(ops node:$src0, node:$src1, node:$src2),
465   [(int_amdgcn_fmad_ftz node:$src0, node:$src1, node:$src2),
466    (AMDGPUfmad_ftz_impl node:$src0, node:$src1, node:$src2)]>;
468 def AMDGPUmul_u24 : PatFrags<(ops node:$src0, node:$src1),
469   [(int_amdgcn_mul_u24 node:$src0, node:$src1),
470    (AMDGPUmul_u24_impl node:$src0, node:$src1)]>;
472 def AMDGPUmul_i24 : PatFrags<(ops node:$src0, node:$src1),
473   [(int_amdgcn_mul_i24 node:$src0, node:$src1),
474    (AMDGPUmul_i24_impl node:$src0, node:$src1)]>;
476 def AMDGPUmulhi_u24 : PatFrags<(ops node:$src0, node:$src1),
477   [(int_amdgcn_mulhi_u24 node:$src0, node:$src1),
478    (AMDGPUmulhi_u24_impl node:$src0, node:$src1)]>;
480 def AMDGPUmulhi_i24 : PatFrags<(ops node:$src0, node:$src1),
481   [(int_amdgcn_mulhi_i24 node:$src0, node:$src1),
482    (AMDGPUmulhi_i24_impl node:$src0, node:$src1)]>;
484 def AMDGPUbfe_i32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
485   [(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),
486    (AMDGPUbfe_i32_impl node:$src0, node:$src1, node:$src2)]>;
488 def AMDGPUbfe_u32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
489   [(int_amdgcn_ubfe node:$src0, node:$src1, node:$src2),
490    (AMDGPUbfe_u32_impl node:$src0, node:$src1, node:$src2)]>;
492 def AMDGPUfmul_legacy : PatFrags<(ops node:$src0, node:$src1),
493   [(int_amdgcn_fmul_legacy node:$src0, node:$src1),
494    (AMDGPUfmul_legacy_impl node:$src0, node:$src1)]>;
496 def AMDGPUfdot2 : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$clamp),
497   [(int_amdgcn_fdot2 node:$src0, node:$src1, node:$src2, node:$clamp),
498    (AMDGPUfdot2_impl node:$src0, node:$src1, node:$src2, node:$clamp)]>;
500 def AMDGPUdiv_fmas : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$vcc),
501   [(int_amdgcn_div_fmas node:$src0, node:$src1, node:$src2, node:$vcc),
502    (AMDGPUdiv_fmas_impl node:$src0, node:$src1, node:$src2, node:$vcc)]>;
504 def AMDGPUperm : PatFrags<(ops node:$src0, node:$src1, node:$src2),
505   [(int_amdgcn_perm node:$src0, node:$src1, node:$src2),
506    (AMDGPUperm_impl node:$src0, node:$src1, node:$src2)]>;