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Searched refs:isWave32 (Results 1 – 25 of 36) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h36 bool isWave32; variable
346 return isWave32 ? &AMDGPU::SReg_32RegClass in getBoolRC()
351 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getWaveMaskRegClass()
H A DSILateBranchLowering.cpp154 MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in runOnMachineFunction()
155 ExecReg = ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in runOnMachineFunction()
H A DSIOptimizeExecMasking.cpp644 ST->isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32 : AMDGPU::S_AND_SAVEEXEC_B64; in tryRecordVCmpxAndSaveexecSequence()
731 ST->isWave32() ? AMDGPU::S_XOR_B32 : AMDGPU::S_XOR_B64; in tryRecordOrSaveexecXorSequence()
741 const unsigned OrSaveexecOpcode = ST->isWave32() in tryRecordOrSaveexecXorSequence()
769 const unsigned Andn2Opcode = ST->isWave32() ? AMDGPU::S_ANDN2_SAVEEXEC_B32 in optimizeOrSaveexecXorSequences()
H A DGCNCreateVOPD.cpp121 if (!AMDGPU::hasVOPD(*ST) || !ST->isWave32()) in runOnMachineFunction()
H A DGCNVOPDUtils.cpp160 if (!AMDGPU::hasVOPD(ST) || !ST.isWave32()) { in apply()
H A DAMDGPUAtomicOptimizer.cpp419 if (ST->isWave32()) { in buildReduction()
492 if (!ST->isWave32()) { in buildScan()
543 if (!ST->isWave32()) { in buildShiftRight()
731 if (ST->isWave32()) { in optimizeAtomic()
H A DSIRegisterInfo.cpp322 SpillSGPRToVGPR(EnableSpillSGPRToVGPR), isWave32(ST.isWave32()) { in SIRegisterInfo()
616 if (isWave32) { in getReservedRegs()
1756 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in spillSGPR()
1879 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); in restoreSGPR()
1958 SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, SGPR, false, 0, in spillEmergencySGPR()
2497 if (!isWave32) in eliminateFrameIndex()
3093 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClassForSizeOnBank()
3118 return isWave32 ? AMDGPU::VCC_LO : AMDGPU::VCC; in getVCC()
3122 return isWave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in getExec()
3137 return isWave32 ? &AMDGPU::SReg_32_XM0_XEXECRegClass in getRegClass()
H A DSIFrameLowering.cpp768 if (ST.isWave32()) { in emitEntryFunctionScratchRsrcRegSetup()
904 ST.isWave32() ? (EnableInactiveLanes ? AMDGPU::S_XOR_SAVEEXEC_B32 in buildScratchExecCopy()
948 unsigned MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillStores()
960 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillStores()
1051 unsigned MovOpc = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillRestores()
1063 unsigned ExecMov = ST.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in emitCSRSpillRestores()
H A DSIInstrInfo.cpp1254 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1268 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1314 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
1332 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32 in insertVectorSelect()
2441 MI.setDesc(get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32 in expandPostRAPseudo()
5383 bool IsWave32 = ST.isWave32(); in insertScratchExecCopy()
5413 MCRegister Exec = isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC; in restoreExec()
6159 ST.isWave32() ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64; in emitLoadScalarOpsFromVGPRLoop()
8892 if (!ST.isWave32()) in fixImplicitOperands()
9361 get(ST.isWave32() ? AMDGPU::S_MOV_B32_term in createPHISourceCopy()
[all …]
H A DGCNSubtarget.h1045 return UserSGPRInit16Bug && isWave32(); in hasUserSGPRInit16Bug()
1424 bool isWave32() const { in isWave32() function
H A DAMDGPUCallLowering.cpp959 bool IsTailCall, bool isWave32, in getCallOpcode() argument
969 return isWave32 ? AMDGPU::SI_CS_CHAIN_TC_W32 : AMDGPU::SI_CS_CHAIN_TC_W64; in getCallOpcode()
1204 getCallOpcode(MF, Info.Callee.isReg(), true, ST.isWave32(), CalleeCC); in lowerTailCall()
1443 unsigned Opc = getCallOpcode(MF, Info.Callee.isReg(), false, ST.isWave32(), in lowerCall()
H A DVOPCInstructions.td232 let WaveSizePredicate = isWave32 in {
995 let WaveSizePredicate = isWave32 in {
1066 let WaveSizePredicate = isWave32 in {
1355 let WaveSizePredicate = isWave32;
1369 let WaveSizePredicate = isWave32;
1387 let WaveSizePredicate = isWave32;
1401 let WaveSizePredicate = isWave32;
1456 let WaveSizePredicate = isWave32;
1472 let WaveSizePredicate = isWave32;
1493 let WaveSizePredicate = isWave32;
[all …]
H A DSIPreEmitPeephole.cpp89 const bool IsWave32 = ST.isWave32(); in optimizeVccBranch()
H A DSIAnnotateControlFlow.cpp129 IntMask = ST.isWave32() ? Type::getInt32Ty(Context) in initialize()
H A DSILowerControlFlow.cpp716 bool IsWave32 = ST.isWave32(); in lowerInitExec()
862 if (ST.isWave32()) { in runOnMachineFunction()
H A DSIShrinkInstructions.cpp766 Op->setReg(ST->isWave32() ? AMDGPU::SGPR_NULL : AMDGPU::SGPR_NULL64); in tryReplaceDeadSDST()
780 unsigned VCCReg = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in runOnMachineFunction()
H A DSIOptimizeExecMaskingPreRA.cpp353 const bool Wave32 = ST.isWave32(); in runOnMachineFunction()
H A DVOPDInstructions.td82 let WaveSizePredicate = isWave32;
H A DSIWholeQuadMode.cpp885 Register VCC = ST->isWave32() ? AMDGPU::VCC_LO : AMDGPU::VCC; in lowerKillF32()
1001 unsigned MovOpc = ST->isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in lowerKillI1()
1601 if (ST->isWave32()) { in runOnMachineFunction()
H A DAMDGPUAsmPrinter.cpp408 if (MF.getSubtarget<GCNSubtarget>().isWave32()) { in getAmdhsaKernelCodeProperties()
1116 if (MD->getPALMajorVersion() < 3 && STM.isWave32()) in EmitPALMetadata()
H A DVOP2Instructions.td289 let WaveSizePredicate = isWave32 in {
358 let WaveSizePredicate = isWave32 in {
1417 let WaveSizePredicate = isWave32;
1445 let WaveSizePredicate = isWave32;
1845 let WaveSizePredicate = isWave32;
1872 let WaveSizePredicate = isWave32;
1897 let WaveSizePredicate = isWave32;
H A DSILowerI1Copies.cpp516 IsWave32 = ST->isWave32(); in PhiLoweringHelper()
H A DVOP3PInstructions.td952 let WaveSizePredicate = isWave32 in {
1241 let WaveSizePredicate = isWave32 in {
1313 let WaveSizePredicate = isWave32, SubtargetPredicate = isGFX12Plus in {
1436 let WaveSizePredicate = isWave32, DecoderNamespace = "GFX12" in {
1569 let WaveSizePredicate = isWave32, DecoderNamespace = "GFX11" in {
H A DAMDGPURegisterBankInfo.cpp787 Subtarget.isWave32() ? AMDGPU::S_MOV_B32 : AMDGPU::S_MOV_B64; in executeInWaterfallLoop()
789 Subtarget.isWave32() ? AMDGPU::S_MOV_B32_term : AMDGPU::S_MOV_B64_term; in executeInWaterfallLoop()
791 const unsigned XorTermOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
793 const unsigned AndSaveExecOpc = Subtarget.isWave32() ? in executeInWaterfallLoop()
795 const unsigned ExecReg = Subtarget.isWave32() ? in executeInWaterfallLoop()
938 {LLT::scalar(Subtarget.isWave32() ? 32 : 64)}) in executeInWaterfallLoop()
H A DSIFixSGPRCopies.cpp1098 bool IsWave32 = MF.getSubtarget<GCNSubtarget>().isWave32(); in fixSCCCopies()

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