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Searched refs:isOperationLegalOrCustom (Results 1 – 20 of 20) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp833 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteFP_TO_INT()
1350 if (TLI.isOperationLegalOrCustom(ISD::SHL, VT) && in ExpandBSWAP()
1351 TLI.isOperationLegalOrCustom(ISD::SRL, VT) && in ExpandBSWAP()
1388 (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) && in ExpandBITREVERSE()
1405 if (TLI.isOperationLegalOrCustom(ISD::SHL, VT) && in ExpandBITREVERSE()
1406 TLI.isOperationLegalOrCustom(ISD::SRL, VT) && in ExpandBITREVERSE()
1546 if (!TLI.isOperationLegalOrCustom(DivOpc, VT) || in ExpandVP_REM()
1547 !TLI.isOperationLegalOrCustom(ISD::VP_MUL, VT) || in ExpandVP_REM()
1548 !TLI.isOperationLegalOrCustom(ISD::VP_SUB, VT)) in ExpandVP_REM()
1692 if (TLI.isOperationLegalOrCustom(ISD::FNEG, VT) && in ExpandFSUB()
[all …]
H A DTargetLowering.cpp1054 if (!TLI.isOperationLegalOrCustom(AVGOpc, VT)) in combineShiftToAVG()
2863 if (isOperationLegalOrCustom(ISD::SHL, VT)) { in SimplifyDemandedBits()
7021 !isOperationLegalOrCustom(ISD::AND, VT) || in prepareSREMEqFold()
7486 isOperationLegalOrCustom(ISD::SRL, VT) && in expandMUL_LOHI()
8139 if (!isOperationLegalOrCustom( in expandFP_TO_UINT()
8288 if (isOperationLegalOrCustom(NewOp, VT)) { in expandFMINNUM_FMAXNUM()
8759 isOperationLegalOrCustom(ISD::CTLZ, VT)) in expandCTLZ()
8879 isOperationLegalOrCustom(ISD::CTTZ, VT)) in expandCTTZ()
10216 if (isOperationLegalOrCustom(LoHiOp, VT)) { in expandFixedPointMul()
10688 if (isOperationLegalOrCustom(DivRemOpc, VT)) { in expandREM()
[all …]
H A DLegalizeDAG.cpp2761 if (!TLI.isOperationLegalOrCustom( in ExpandLegalINT_TO_FP()
2860 if (TLI.isOperationLegalOrCustom(SIntOp, NewInTy)) { in PromoteLegalINT_TO_FP()
2868 if (TLI.isOperationLegalOrCustom(UIntOp, NewInTy)) { in PromoteLegalINT_TO_FP()
2960 if (TLI.isOperationLegalOrCustom(Opcode, NewOutTy)) in PromoteLegalFP_TO_INT_SAT()
3677 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) && in ExpandNode()
3678 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) { in ExpandNode()
3706 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) { in ExpandNode()
3734 if (TLI.isOperationLegalOrCustom(MULHOpcode, VT)) { in ExpandNode()
3791 TLI.isOperationLegalOrCustom(ISD::SHL, VT) && in ExpandNode()
3792 TLI.isOperationLegalOrCustom(ISD::OR, VT) && in ExpandNode()
[all …]
H A DDAGCombiner.cpp912 bool isOperationLegalOrCustom(unsigned Op, EVT VT, in isOperationLegalOrCustom() function in __anonffc06dc60111::EmptyMatchContext
1020 bool isOperationLegalOrCustom(unsigned Op, EVT VT, in isOperationLegalOrCustom() function in __anonffc06dc60111::VPMatchContext
3874 !TLI.isOperationLegalOrCustom(ISD::ABS, VT)) in visitSUB()
4066 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) { in visitSUB()
4648 if (TLI.isOperationLegalOrCustom(Opcode, VT)) in useDivRem()
7597 if (!TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) in matchBSwapHWordOrAndAnd()
7690 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) in MatchBSwapHWord()
7692 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) in MatchBSwapHWord()
9533 if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) { in visitXOR()
13547 TLI.isOperationLegalOrCustom(ISD::SUB, VT)) { in visitSIGN_EXTEND()
[all …]
H A DLegalizeIntegerTypes.cpp734 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT)) in PromoteIntRes_FP_TO_XINT()
744 TLI.isOperationLegalOrCustom(ISD::VP_FP_TO_SINT, NVT)) in PromoteIntRes_FP_TO_XINT()
1411 !TLI.isOperationLegalOrCustom(Opcode, VT)) { in PromoteIntRes_FunnelShift()
1463 !TLI.isOperationLegalOrCustom(Opcode, VT)) { in PromoteIntRes_VPFunnelShift()
2453 TLI.isOperationLegalOrCustom(ISD::VECREDUCE_ADD, InVT)) in PromoteIntOp_VECREDUCE()
3206 bool HasOpCarry = TLI.isOperationLegalOrCustom( in ExpandIntRes_ADDSUB()
3233 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? in ExpandIntRes_ADDSUB()
3252 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? in ExpandIntRes_ADDSUB()
3407 bool HasCarryOp = TLI.isOperationLegalOrCustom( in ExpandIntRes_UADDSUBO()
3620 bool HasSubCarry = TLI.isOperationLegalOrCustom( in ExpandIntRes_ABS()
[all …]
H A DSelectionDAGBuilder.cpp3541 !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT); in visitSelect()
3560 if (TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT) || in visitSelect()
3562 TLI.isOperationLegalOrCustom(ISD::FMINNUM, VT.getScalarType()))) in visitSelect()
3573 if (TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT) || in visitSelect()
3575 TLI.isOperationLegalOrCustom(ISD::FMAXNUM, VT.getScalarType()))) in visitSelect()
3593 TLI.isOperationLegalOrCustom(Opc, VT.getScalarType()))) && in visitSelect()
6683 if (!TLI.isOperationLegalOrCustom(ISD::IS_FPCLASS, ArgVT)) { in visitIntrinsicCall()
6701 if (TLI.isOperationLegalOrCustom(ISD::GET_FPENV, EnvVT)) { in visitIntrinsicCall()
6730 if (TLI.isOperationLegalOrCustom(ISD::SET_FPENV, EnvVT)) { in visitIntrinsicCall()
H A DLegalizeVectorTypes.cpp4056 if (!TLI.isOperationLegalOrCustom(N->getOpcode(), WideVecVT) && in WidenVectorResult()
5367 TLI.isOperationLegalOrCustom(ISD::VP_LOAD, WideVT) && in WidenVecRes_LOAD()
6492 if (TLI.isOperationLegalOrCustom(ISD::VP_STORE, WideVT) && in WidenVecOp_STORE()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsTargetTransformInfo.cpp15 return TLI->isOperationLegalOrCustom(IsSigned ? ISD::SDIVREM : ISD::UDIVREM, in hasDivRemOp()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h498 return TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || in shouldBuildLookupTables()
499 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other); in shouldBuildLookupTables()
531 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT); in haveFastSqrt()
925 if (TLI->isOperationLegalOrCustom(IsSigned ? ISD::SDIVREM : ISD::UDIVREM,
927 TLI->isOperationLegalOrCustom(IsSigned ? ISD::SDIV : ISD::UDIV,
H A DTargetLowering.h1276 bool isOperationLegalOrCustom(unsigned Op, EVT VT,
1326 return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || in areJTsAllowed()
1327 isOperationLegalOrCustom(ISD::BRIND, MVT::Other); in areJTsAllowed()
3276 return isOperationLegalOrCustom(Op, VT); in shouldConvertFpToSat()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1180 return Op != ISD::FP_TO_UINT_SAT && isOperationLegalOrCustom(Op, VT); in shouldConvertFpToSat()
H A DX86ISelLowering.cpp3107 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
7408 if (!TLI.isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT)) in buildFromShuffleMostly()
8763 (isOperationLegalOrCustom(ISD::INSERT_VECTOR_ELT, VT) || in LowerBUILD_VECTOR()
8764 isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))) { in LowerBUILD_VECTOR()
44661 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT)) in combineVSelectToBLENDV()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp2090 if (TLI.isOperationLegalOrCustom( in SinkShiftAndTruncate()
4272 return TLI.isOperationLegalOrCustom( in isPromotedInstructionLegal()
7679 TLI.isOperationLegalOrCustom( in shouldPromote()
8368 !TLI->isOperationLegalOrCustom(ISD::BITREVERSE, in makeBitReverse()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp2821 if (TLI->isOperationLegalOrCustom(ISD::MULHU, VT)) { in getArithmeticInstrCost()
2838 if (TLI->isOperationLegalOrCustom(ISD, LT.second) && ST->hasSVE()) { in getArithmeticInstrCost()
H A DAArch64ISelLowering.cpp14749 isOperationLegalOrCustom(ISD::FMA, getValueType(DL, Ty)) && in isProfitableToHoist()
16467 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp2154 return isOperationLegalOrCustom(ISD::FMA, VT); in isFMAFasterThanFMulAndFAdd()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2142 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
4592 if (!Subtarget.getTargetLowering()->isOperationLegalOrCustom(ISD::BITREVERSE, in lowerBitreverseShuffle()
14707 if (!TLI.isOperationLegalOrCustom(Opcode, VT) || !TLI.isTypeLegal(VT)) in performBUILD_VECTORCombine()
19524 if (!isOperationLegalOrCustom(Op, VT) || !FPVT.isSimple()) in shouldConvertFpToSat()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp8424 isOperationLegalOrCustom(Op.getOpcode(), in canReuseLoadAddress()
17336 isOperationLegalOrCustom(ISD::FMA, getValueType(DL, Ty)) && in isProfitableToHoist()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp13891 if (!isOperationLegalOrCustom(Op, VT) || !FPVT.isSimple()) in shouldConvertFpToSat()
21234 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp1869 if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT)) in isExtractSubvectorCheap()