242         if (isOperationLegalOrCustom(ISD::STORE, NewVT) &&  in findOptimalMemOpLowering()
246                  isOperationLegalOrCustom(ISD::STORE, MVT::f64) &&  in findOptimalMemOpLowering()
1051   if (!TLI.isOperationLegalOrCustom(AVGOpc, NVT)) {  in combineShiftToAVG()
1054     if (!TLI.isOperationLegalOrCustom(AVGOpc, VT))  in combineShiftToAVG()
2658       bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, VT);  in SimplifyDemandedBits()
2659       bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32);  in SimplifyDemandedBits()
2863     if (isOperationLegalOrCustom(ISD::SHL, VT)) {  in SimplifyDemandedBits()
5137     if (isOperationLegalOrCustom(ISD::IS_FPCLASS, N0.getValueType()) &&  in SimplifySetCC()
6263     if (isOperationLegalOrCustom(ISD::MULHS, VT, IsAfterLegalization))  in BuildSDIV()
6265     if (isOperationLegalOrCustom(ISD::SMUL_LOHI, VT, IsAfterLegalization)) {  in BuildSDIV()
6276     if (isOperationLegalOrCustom(ISD::MUL, WideVT)) {  in BuildSDIV()
6449     if (isOperationLegalOrCustom(ISD::MULHU, VT, IsAfterLegalization))  in BuildUDIV()
6451     if (isOperationLegalOrCustom(ISD::UMUL_LOHI, VT, IsAfterLegalization)) {  in BuildUDIV()
6462     if (isOperationLegalOrCustom(ISD::MUL, WideVT)) {  in BuildUDIV()
6579   if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT))  in prepareUREMEqFold()
6716     if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::SUB, VT))  in prepareUREMEqFold()
6731     if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT))  in prepareUREMEqFold()
6761   if (isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) {  in prepareUREMEqFold()
6773   if (isOperationLegalOrCustom(ISD::XOR, SETCCVT))  in prepareUREMEqFold()
6829   if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT))  in prepareSREMEqFold()
6984     if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ADD, VT))  in prepareSREMEqFold()
6996     if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT))  in prepareSREMEqFold()
7020   if (!isOperationLegalOrCustom(ISD::SETCC, SETCCVT) ||  in prepareSREMEqFold()
7021       !isOperationLegalOrCustom(ISD::AND, VT) ||  in prepareSREMEqFold()
7023       !isOperationLegalOrCustom(ISD::VSELECT, SETCCVT))  in prepareSREMEqFold()
7192     if (LegalOps && !isOperationLegalOrCustom(ISD::FSUB, VT))  in getNegatedExpression()
7409                   isOperationLegalOrCustom(ISD::MULHS, HiLoVT);  in expandMUL_LOHI()
7411                   isOperationLegalOrCustom(ISD::MULHU, HiLoVT);  in expandMUL_LOHI()
7413                       isOperationLegalOrCustom(ISD::SMUL_LOHI, HiLoVT);  in expandMUL_LOHI()
7415                       isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT);  in expandMUL_LOHI()
7446       isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {  in expandMUL_LOHI()
7486       isOperationLegalOrCustom(ISD::SRL, VT) &&  in expandMUL_LOHI()
7487       isOperationLegalOrCustom(ISD::TRUNCATE, HiLoVT)) {  in expandMUL_LOHI()
7533   bool UseGlue = (isOperationLegalOrCustom(ISD::ADDC, VT) &&  in expandMUL_LOHI()
7534                   isOperationLegalOrCustom(ISD::ADDE, VT));  in expandMUL_LOHI()
7642   if (!isOperationLegalOrCustom(ISD::MULHU, HiLoVT) &&  in expandDIVREMByConstant()
7643       !isOperationLegalOrCustom(ISD::UMUL_LOHI, HiLoVT))  in expandDIVREMByConstant()
7698     if (isOperationLegalOrCustom(ISD::UADDO_CARRY, HiLoVT)) {  in expandDIVREMByConstant()
7840   if (VT.isVector() && (!isOperationLegalOrCustom(ISD::SHL, VT) ||  in expandFunnelShift()
7841                         !isOperationLegalOrCustom(ISD::SRL, VT) ||  in expandFunnelShift()
7842                         !isOperationLegalOrCustom(ISD::SUB, VT) ||  in expandFunnelShift()
7858   if (!isOperationLegalOrCustom(Node->getOpcode(), VT) &&  in expandFunnelShift()
7859       isOperationLegalOrCustom(RevOpcode, VT) && isPowerOf2_32(BW)) {  in expandFunnelShift()
7936   if (!isOperationLegalOrCustom(Node->getOpcode(), VT) &&  in expandROT()
7937       isOperationLegalOrCustom(RevRot, VT) && isPowerOf2_32(EltSizeInBits)) {  in expandROT()
7943       (!isOperationLegalOrCustom(ISD::SHL, VT) ||  in expandROT()
7944        !isOperationLegalOrCustom(ISD::SRL, VT) ||  in expandROT()
7945        !isOperationLegalOrCustom(ISD::SUB, VT) ||  in expandROT()
8117   if (DstVT.isVector() && (!isOperationLegalOrCustom(SIntOpcode, DstVT) ||  in expandFP_TO_UINT()
8139   if (!isOperationLegalOrCustom(  in expandFP_TO_UINT()
8219   if (SrcVT.isVector() && (!isOperationLegalOrCustom(ISD::SRL, SrcVT) ||  in expandUINT_TO_FP()
8220                            !isOperationLegalOrCustom(ISD::FADD, DstVT) ||  in expandUINT_TO_FP()
8221                            !isOperationLegalOrCustom(ISD::FSUB, DstVT) ||  in expandUINT_TO_FP()
8288   if (isOperationLegalOrCustom(NewOp, VT)) {  in expandFMINNUM_FMAXNUM()
8319     if (isOperationLegalOrCustom(IEEE2018Op, VT))  in expandFMINNUM_FMAXNUM()
8392       isOperationLegalOrCustom(ISD::SETCC, OperandVT.getScalarType())) {  in expandIS_FPCLASS()
8419         isOperationLegalOrCustom(ISD::FABS, OperandVT.getScalarType())) {  in expandIS_FPCLASS()
8619   return TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&  in canExpandVectorCTPOP()
8620          TLI.isOperationLegalOrCustom(ISD::SUB, VT) &&  in canExpandVectorCTPOP()
8621          TLI.isOperationLegalOrCustom(ISD::SRL, VT) &&  in canExpandVectorCTPOP()
8622          (Len == 8 || TLI.isOperationLegalOrCustom(ISD::MUL, VT)) &&  in canExpandVectorCTPOP()
8759       isOperationLegalOrCustom(ISD::CTLZ, VT))  in expandCTLZ()
8763   if (isOperationLegalOrCustom(ISD::CTLZ_ZERO_UNDEF, VT)) {  in expandCTLZ()
8776                         (!isOperationLegalOrCustom(ISD::CTPOP, VT) &&  in expandCTLZ()
8778                         !isOperationLegalOrCustom(ISD::SRL, VT) ||  in expandCTLZ()
8879       isOperationLegalOrCustom(ISD::CTTZ, VT))  in expandCTTZ()
8883   if (isOperationLegalOrCustom(ISD::CTTZ_ZERO_UNDEF, VT)) {  in expandCTTZ()
8896                         (!isOperationLegalOrCustom(ISD::CTPOP, VT) &&  in expandCTTZ()
8897                          !isOperationLegalOrCustom(ISD::CTLZ, VT) &&  in expandCTTZ()
8899                         !isOperationLegalOrCustom(ISD::SUB, VT) ||  in expandCTTZ()
8978       (!isOperationLegalOrCustom(ISD::SRA, VT) ||  in expandABS()
8979        (!IsNegative && !isOperationLegalOrCustom(ISD::ADD, VT)) ||  in expandABS()
8980        (IsNegative && !isOperationLegalOrCustom(ISD::SUB, VT)) ||  in expandABS()
9469       if (!isOperationLegalOrCustom(ISD::LOAD, intVT) &&  in expandUnalignedLoad()
9623       if (!isOperationLegalOrCustom(ISD::STORE, intVT) &&  in expandUnalignedStore()
9951   if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT))  in expandIntMINMAX()
10041   if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT))  in expandAddSubSat()
10127   if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT))  in expandShlSat()
10175       if (isOperationLegalOrCustom(ISD::MUL, VT))  in expandFixedPointMul()
10177     } else if (Signed && isOperationLegalOrCustom(ISD::SMULO, VT)) {  in expandFixedPointMul()
10194     } else if (!Signed && isOperationLegalOrCustom(ISD::UMULO, VT)) {  in expandFixedPointMul()
10216   if (isOperationLegalOrCustom(LoHiOp, VT)) {  in expandFixedPointMul()
10220   } else if (isOperationLegalOrCustom(HiOp, VT)) {  in expandFixedPointMul()
10353         isOperationLegalOrCustom(ISD::SDIVREM, VT)) {  in expandFixedPointDiv()
10391   if (isOperationLegalOrCustom(OpcCarry, Node->getValueType(0))) {  in expandUADDSUBO()
10505   if (isOperationLegalOrCustom(Ops[isSigned][0], VT)) {  in expandMULO()
10508   } else if (isOperationLegalOrCustom(Ops[isSigned][1], VT)) {  in expandMULO()
10626       if (!isOperationLegalOrCustom(BaseOpcode, HalfVT))  in expandVecReduce()
10688   if (isOperationLegalOrCustom(DivRemOpc, VT)) {  in expandREM()
10693   if (isOperationLegalOrCustom(DivOpc, VT)) {  in expandREM()