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Searched refs:isInt (Results 1 – 25 of 221) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParserCommon.h17 return isInt<8>(Value) || in isImmSExti16i8Value()
18 (isUInt<16>(Value) && isInt<8>(static_cast<int16_t>(Value))); in isImmSExti16i8Value()
22 return isInt<8>(Value) || in isImmSExti32i8Value()
23 (isUInt<32>(Value) && isInt<8>(static_cast<int32_t>(Value))); in isImmSExti32i8Value()
27 return isInt<8>(Value); in isImmSExti64i8Value()
31 return isInt<32>(Value); in isImmSExti64i32Value()
35 return isUInt<8>(Value) || isInt<8>(Value); in isImmUnsignedi8Value()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp31 Compressed = isInt<6>(Instr.getImm()); in getInstSeqCost()
54 (!isInt<32>(Val) || Val == 0x800)) { in generateInstSeqImpl()
59 if (isInt<32>(Val)) { in generateInstSeqImpl()
112 if (!isInt<32>(Val)) { in generateInstSeqImpl()
118 if (ShiftAmount > 12 && !isInt<12>(Val)) { in generateInstSeqImpl()
119 if (isInt<32>((uint64_t)Val << 12)) { in generateInstSeqImpl()
329 if (isInt<32>(NewVal)) { in generateInstSeq()
371 if ((Val % 3) == 0 && isInt<32>(Val / 3)) { in generateInstSeq()
374 } else if ((Val % 5) == 0 && isInt<32>(Val / 5)) { in generateInstSeq()
393 if (isInt<32>(Hi52 / 3) && (Hi52 % 3) == 0) { in generateInstSeq()
[all …]
H A DRISCVAsmBackend.cpp175 return !isInt<13>(Offset); in fixupNeedsRelaxationAdvanced()
435 if (!isInt<12>(Value)) { in adjustFixupValue()
450 if (!isInt<21>(Value)) in adjustFixupValue()
467 if (!isInt<13>(Value)) in adjustFixupValue()
494 if (!isInt<12>(Value)) in adjustFixupValue()
510 if (!isInt<9>(Value)) in adjustFixupValue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsAsmBackend.cpp81 if (!isInt<16>(Value)) { in adjustFixupValue()
91 if (!isInt<19>(Value)) { in adjustFixupValue()
130 if (!isInt<7>(Value)) { in adjustFixupValue()
140 if (!isInt<10>(Value)) { in adjustFixupValue()
150 if (!isInt<16>(Value)) { in adjustFixupValue()
159 if (!isInt<18>(Value)) { in adjustFixupValue()
172 if (!isInt<18>(Value)) { in adjustFixupValue()
181 if (!isInt<21>(Value)) { in adjustFixupValue()
190 if (!isInt<26>(Value)) { in adjustFixupValue()
199 if (!isInt<26>(Value)) { in adjustFixupValue()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/
H A DXtensaAsmBackend.cpp95 if (!isInt<6>(Value)) in adjustFixupValue()
103 if (!isInt<8>(Value)) in adjustFixupValue()
108 if (!isInt<12>(Value)) in adjustFixupValue()
113 if (!isInt<18>(Value)) in adjustFixupValue()
118 if (!isInt<20>(Value)) in adjustFixupValue()
127 if (!isInt<18>(Value) && (Value & 0x20000)) in adjustFixupValue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp319 return isInt<18>(BrOffset); in isBranchOffsetInRange()
335 return isInt<17>(BrOffset); in isBranchOffsetInRange()
339 return isInt<11>(BrOffset); in isBranchOffsetInRange()
343 return isInt<8>(BrOffset); in isBranchOffsetInRange()
348 return isInt<28>(BrOffset); in isBranchOffsetInRange()
372 return isInt<18>(BrOffset); in isBranchOffsetInRange()
376 return isInt<23>(BrOffset); in isBranchOffsetInRange()
380 return isInt<11>(BrOffset); in isBranchOffsetInRange()
384 return isInt<8>(BrOffset); in isBranchOffsetInRange()
388 return isInt<27>(BrOffset); in isBranchOffsetInRange()
[all …]
H A DMips16InstrInfo.cpp232 if (isInt<16>(-Remainder)) in makeFrame()
258 if (isInt<16>(Remainder)) in restoreFrame()
312 if (isInt<16>(Amount)) // need to change to addiu sp, ....and isInt<16> in adjustStackPtr()
483 return isInt<16>(Amount); in validImmediate()
486 return isInt<16>(Amount); in validImmediate()
487 return isInt<15>(Amount); in validImmediate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiTargetTransformInfo.h67 if (isInt<16>(Imm.getSExtValue())) in getIntImmCost()
69 if (isInt<21>(Imm.getZExtValue())) in getIntImmCost()
71 if (isInt<32>(Imm.getSExtValue())) { in getIntImmCost()
H A DLanaiISelDAGToDAG.cpp97 return isInt<21>(CN.getSExtValue()) && ((CN.getSExtValue() & 0x3) == 0); in canBeRepresentedAsSls()
134 if (isInt<16>(CN->getSExtValue())) { in selectAddrRiSpls()
147 if (isInt<10>(CN->getSExtValue())) { in selectAddrRiSpls()
178 if ((RiMode && isInt<16>(CN->getSExtValue())) || in selectAddrRiSpls()
179 (!RiMode && isInt<10>(CN->getSExtValue()))) { in selectAddrRiSpls()
264 if (isInt<16>(CN->getSExtValue())) in selectAddrRr()
H A DLanaiRegisterInfo.cpp165 if ((isSPLSOpcode(MI.getOpcode()) && !isInt<10>(Offset)) || in eliminateFrameIndex()
166 !isInt<16>(Offset)) { in eliminateFrameIndex()
181 if (!isInt<16>(Offset)) { in eliminateFrameIndex()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/ExecutionEngine/JITLink/
H A Dppc64.h386 if (LLVM_UNLIKELY(!isInt<32>(Value))) { in applyFixup()
407 if (LLVM_UNLIKELY(!isInt<32>(Value))) { in applyFixup()
416 if (LLVM_UNLIKELY(!isInt<16>(Value))) { in applyFixup()
431 if (LLVM_UNLIKELY(!isInt<32>(Value))) { in applyFixup()
439 if (LLVM_UNLIKELY(!isInt<26>(Value))) { in applyFixup()
462 if (!LLVM_UNLIKELY(isInt<34>(Value))) in applyFixup()
474 if (LLVM_UNLIKELY(!isInt<32>(Value))) { in applyFixup()
482 if (LLVM_UNLIKELY(!isInt<32>(Value))) { in applyFixup()
H A Dloongarch.h196 if (!isInt<28>(Value)) in applyFixup()
212 if (!isInt<32>(Value)) in applyFixup()
219 if (!isInt<32>(Value)) in applyFixup()
234 if (!isInt<32>(PageDelta)) in applyFixup()
H A Dx86_64.h420 if (LLVM_LIKELY(isInt<32>(Value))) in applyFixup()
454 if (LLVM_LIKELY(isInt<32>(Value))) in applyFixup()
469 if (LLVM_LIKELY(isInt<32>(Value))) in applyFixup()
484 if (LLVM_LIKELY(isInt<32>(Value))) in applyFixup()
H A Daarch64.h517 if (!isInt<21>(Delta)) in applyFixup()
536 if (!isInt<16>(Delta)) in applyFixup()
554 if (!isInt<21>(Delta)) in applyFixup()
569 if (!isInt<33>(PageDelta)) in applyFixup()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonOperands.td13 def s8_0Imm64Pred : PatLeaf<(i64 imm), [{ return isInt<8>(N->getSExtValue()); }]>;
20 return isInt<32>(v);
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp67 else if (isInt<12>(AbsAmount)) in generateStackAdjustment()
140 else if (isInt<12>(VarArgsBytes)) in emitPrologue()
285 else if (isInt<12>(MoveAmount)) in emitEpilogue()
300 else if (isInt<12>(4 * StackSlotsUsedByFunclet)) in emitEpilogue()
327 else if (isInt<12>(VarArgsBytes)) in emitEpilogue()
457 else if (isInt<12>(NumBytes)) in emitRegUpdate()
H A DARCISelDAGToDAG.cpp112 if (!isInt<9>(RHSC)) in SelectAddrModeS9()
175 isInt<12>(CVal) ? ARC::MOV_rs12 : ARC::MOV_rlimm, in Select()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVCodeGenPrepare.cpp92 if (!isUInt<32>(C) || isInt<12>(C) || !isInt<12>(SignExtend64<32>(C))) in visitAnd()
H A DRISCVMergeBaseOffset.cpp140 assert(isInt<32>(Offset) && "Unexpected offset"); in foldOffset()
218 if (!isInt<32>(Offset)) in foldLargeOffset()
277 assert(isInt<12>(Offset) && "Unexpected offset"); in foldShiftedOffset()
464 if (!isInt<32>(NewOffset)) in foldIntoMemoryOps()
H A DRISCVISelDAGToDAG.cpp625 if (isInt<12>(Val)) in tryShrinkShlLogicImm()
656 if (!isInt<12>(ShiftedVal)) in tryShrinkShlLogicImm()
1122 const bool isC1ANDI = isInt<12>(C1); in Select()
1373 isInt<12>(C2) || in Select()
2245 if (isInt<12>(CVal)) { in SelectFrameAddrRegImm()
2404 if (isInt<12>(CVal) && isInt<12>(CVal + RV32ZdinxRange)) { in SelectAddrRegImm()
2438 assert(!(isInt<12>(CVal) && isInt<12>(CVal + RV32ZdinxRange)) && in SelectAddrRegImm()
2444 if (isInt<12>(CVal / 2) && isInt<12>(CVal - CVal / 2)) { in SelectAddrRegImm()
2491 if (isInt<12>(CVal)) { in SelectAddrRegImmLsb00000()
2511 assert(!(isInt<12>(CVal) && isInt<12>(CVal)) && in SelectAddrRegImmLsb00000()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/ExecutionEngine/JITLink/
H A Dx86_64.cpp108 bool DisplacementInRangeForImmS32 = isInt<32>(Displacement); in optimizeGOTAndStubAccesses()
178 if (isInt<32>(Displacement)) { in optimizeGOTAndStubAccesses()
H A Daarch32.cpp482 if (!isInt<32>(Value)) in applyFixupData()
502 if (!isInt<31>(Value)) in applyFixupData()
543 if (!isInt<26>(Value)) in applyFixupArm()
573 if (!isInt<26>(Value)) in applyFixupArm()
619 if (!isInt<25>(Value)) in applyFixupThumb()
623 if (!isInt<22>(Value)) in applyFixupThumb()
652 if (!isInt<25>(Value)) in applyFixupThumb()
656 if (!isInt<22>(Value)) in applyFixupThumb()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp189 if (!STI.is64Bit() && !isInt<32>(Val)) in movImm()
323 return isInt<18>(BrOffset); in isBranchOffsetInRange()
328 return isInt<23>(BrOffset); in isBranchOffsetInRange()
331 return isInt<28>(BrOffset); in isBranchOffsetInRange()
423 if (!isInt<32>(BrOffset)) in insertIndirectBranch()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/MCTargetDesc/
H A DM68kAsmBackend.cpp173 if (!isInt<16>(Value)) { in fixupNeedsRelaxation()
183 return Value == 0 || !isInt<8>(Value); in fixupNeedsRelaxation()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelDAGToDAG.cpp160 isInt<16>(IMMOffset->getZExtValue())) { in SelectADDRVTX_READ()
168 isInt<16>(IMMOffset->getZExtValue())) { in SelectADDRVTX_READ()

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