625   if (isInt<12>(Val))  in tryShrinkShlLogicImm()
634   if (isInt<32>(Val) && N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&  in tryShrinkShlLogicImm()
656   if (!isInt<12>(ShiftedVal))  in tryShrinkShlLogicImm()
776     if (isInt<5>(Offset >> Shift) && ((Offset % (1LL << Shift)) == 0))  in tryIndexedLoad()
850     if (isUInt<16>(Imm) && isInt<12>(SignExtend64<16>(Imm)) &&  in Select()
855     if (!isInt<32>(Imm) && isUInt<32>(Imm) && hasAllWUsers(Node))  in Select()
1122     const bool isC1ANDI = isInt<12>(C1);  in Select()
1154       bool IsCANDI = isInt<6>(N1C->getSExtValue());  in Select()
1373         isInt<12>(C2) ||  in Select()
1377     if (IsANDIOrZExt && (isInt<12>(N1C->getSExtValue()) || !N0.hasOneUse()))  in Select()
1384     if (IsZExtW && (isInt<32>(N1C->getSExtValue()) || !N0.hasOneUse()))  in Select()
2245     if (isInt<12>(CVal)) {  in SelectFrameAddrRegImm()
2272   if (!Subtarget->is64Bit() || isInt<32>(Hi)) {  in selectConstantAddr()
2361           isInt<12>(C1->getSExtValue())) {  in SelectAddrRegRegScale()
2404     if (isInt<12>(CVal) && isInt<12>(CVal + RV32ZdinxRange)) {  in SelectAddrRegImm()
2438     assert(!(isInt<12>(CVal) && isInt<12>(CVal + RV32ZdinxRange)) &&  in SelectAddrRegImm()
2444     if (isInt<12>(CVal / 2) && isInt<12>(CVal - CVal / 2)) {  in SelectAddrRegImm()
2491     if (isInt<12>(CVal)) {  in SelectAddrRegImmLsb00000()
2511     assert(!(isInt<12>(CVal) && isInt<12>(CVal)) &&  in SelectAddrRegImmLsb00000()
2664     if (isInt<12>(CVal) || CVal == 2048) {  in selectSETCC()
3063       if (isInt<5>(Offset >> Shift) && ((Offset % (1LL << Shift)) == 0))  in selectSimm5Shl2()
3161                                [](int64_t Imm) { return isInt<5>(Imm); });  in selectVSplatSimm5()
3167       [](int64_t Imm) { return (isInt<5>(Imm) && Imm != -16) || Imm == 16; });  in selectVSplatSimm5Plus1()
3174         return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);  in selectVSplatSimm5Plus1NonZero()
3246     if (!isInt<5>(ImmVal))  in selectRVVSimm5()