Searched refs:hasV6Ops (Results 1 – 11 of 11) sorted by relevance
141 return hasV6Ops() && hasARMOps() && !isTargetWindows(); in isXRaySupported()446 if (!hasV6Ops()) in useFastISel()
50 if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg) in copyPhysReg()
17 def HasV6 : Predicate<"Subtarget->hasV6Ops()">,19 def NoV6 : Predicate<"!Subtarget->hasV6Ops()">;
339 return HasDataBarrier || (hasV6Ops() && !isThumb()); in hasAnyDataBarrier()
2688 bool hasV6Ops = Subtarget->hasV6Ops(); in ARMEmitIntExt() local2692 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt]; in ARMEmitIntExt()
1214 if (!Subtarget->hasV6Ops()) in ARMTargetLowering()1402 if (!Subtarget->hasV6Ops()) { in ARMTargetLowering()1593 if (Subtarget->hasV6Ops()) in ARMTargetLowering()13062 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP()) in AddCombineTo64bitUMAAL()13110 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP()) in PerformUMLALCombine()14452 if (!Subtarget->hasV6Ops() || in PerformORCombineToSMULWBT()20298 if (!Subtarget->hasV6Ops()) in ExpandInlineAsm()21325 has64BitAtomicStore = Subtarget->hasV6Ops(); in shouldExpandAtomicStoreInIR()21347 has64BitAtomicLoad = Subtarget->hasV6Ops(); in shouldExpandAtomicLoadInIR()21368 hasAtomicRMW = Subtarget->hasV6Ops(); in shouldExpandAtomicRMWInIR()[all …]
3948 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()3967 Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl, in Select()3973 if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP()) in Select()
438 if (Inst && ((ST->hasV6Ops() && !ST->isThumb()) || ST->isThumb2()) && in getIntImmCostInst()
741 !STI->hasV6Ops()) { in CreateLoadStoreMulti()
4847 if (MI.getOpcode() == ARM::tMOVr && !Subtarget.hasV6Ops()) { in verifyInstruction()
543 bool hasV6Ops() const { in hasV6Ops() function in __anon2f82d7160111::ARMAsmParser10935 else if (Opc == ARM::tMOVr && !hasV6Ops() && in checkTargetMatchPredicate()