1164   if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()  in ARMTargetLowering()
1214   if (!Subtarget->hasV6Ops())  in ARMTargetLowering()
1375       (!Subtarget->isMClass() && Subtarget->hasV6Ops())) {  in ARMTargetLowering()
1402   if (!Subtarget->hasV6Ops()) {  in ARMTargetLowering()
1593   if (Subtarget->hasV6Ops())  in ARMTargetLowering()
1598   if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) ||  in ARMTargetLowering()
1952       (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? Align(8) : Align(4));  in shouldAlignPointerArgs()
4257     assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&  in LowerATOMIC_FENCE()
5065   if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP() || Subtarget->isThumb1Only())  in LowerADDSUBSAT()
5416   if ((!Subtarget->isThumb() && Subtarget->hasV6Ops()) || Subtarget->isThumb2())  in LowerSELECT_CC()
13015   if (Subtarget->hasV6Ops() && Subtarget->hasDSP() && Subtarget->useMulOps() &&  in AddCombineTo64bitMLAL()
13062   if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())  in AddCombineTo64bitUMAAL()
13110   if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP())  in PerformUMLALCombine()
14452   if (!Subtarget->hasV6Ops() ||  in PerformORCombineToSMULWBT()
17912   if ((Subtarget->isThumb() || !Subtarget->hasV6Ops()) &&  in PerformMinMaxToSatCombine()
20298   if (!Subtarget->hasV6Ops())  in ExpandInlineAsm()
21249     if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {  in makeDMB()
21325     has64BitAtomicStore = Subtarget->hasV6Ops();  in shouldExpandAtomicStoreInIR()
21347     has64BitAtomicLoad = Subtarget->hasV6Ops();  in shouldExpandAtomicLoadInIR()
21368     hasAtomicRMW = Subtarget->hasV6Ops();  in shouldExpandAtomicRMWInIR()
21398     HasAtomicCmpXchg = Subtarget->hasV6Ops();  in shouldExpandAtomicCmpXchgInIR()