Searched refs:has16BitInsts (Results 1 – 9 of 9) sorted by relevance
340 return (ElemWidth == 16 && ST->has16BitInsts()) ? 2 in getMaximumVF()553 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()568 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()579 if (ST->has16BitInsts() && SLT == MVT::i16) in getArithmeticInstrCost()595 if (ST->has16BitInsts() && SLT == MVT::f16 && !HasFP64FP16Denormals) in getArithmeticInstrCost()614 if (ST->has16BitInsts() && SLT == MVT::f16) in getArithmeticInstrCost()638 (SLT == MVT::f16 && ST->has16BitInsts())) { in getArithmeticInstrCost()643 if (SLT == MVT::f16 && ST->has16BitInsts()) { in getArithmeticInstrCost()727 if ((ST->has16BitInsts() && SLT == MVT::f16) || in getIntrinsicInstrCost()825 if (EltSize == 16 && Index == 0 && ST->has16BitInsts()) in getVectorInstrCost()
154 bool has16BitInsts() const { in has16BitInsts() function
423 (Ty->isHalfTy() && ST->has16BitInsts()); in isLegalFloatingTy()633 if (Size <= 16 && ST->has16BitInsts()) in replaceMulWithMul24()1543 if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) && in visitBinaryOperator()1672 if (ST->has16BitInsts() && needsPromotionToI32(I.getOperand(0)->getType()) && in visitICmpInst()1686 if (ST->has16BitInsts() && needsPromotionToI32(I.getType())) { in visitSelectInst()2029 if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) && in visitBitreverseIntrinsicInst()2122 if (!Ty->isFloatTy() && (!Ty->isHalfTy() || ST->has16BitInsts())) in visitSqrt()
891 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()946 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()1014 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()1044 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()1075 if (ST.has16BitInsts()) in AMDGPULegalizerInfo()1086 if (ST.has16BitInsts()) in AMDGPULegalizerInfo()1106 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()1154 if (ST.has16BitInsts()) { in AMDGPULegalizerInfo()1178 if (ST.has16BitInsts()) in AMDGPULegalizerInfo()1191 if (ST.has16BitInsts()) in AMDGPULegalizerInfo()[all …]
360 if (Subtarget->has16BitInsts()) in AMDGPUTargetLowering()907 (Subtarget->has16BitInsts() && VT == MVT::f16); in isFAbsFree()950 if (DestSize== 16 && Subtarget->has16BitInsts()) in isTruncateFree()960 if (SrcSize == 16 && Subtarget->has16BitInsts()) in isZExtFree()2622 assert(!Subtarget->has16BitInsts()); in LowerFLOG2()2663 if (VT == MVT::f16 && !Subtarget->has16BitInsts()) { in LowerFLOGCommon()2669 if (VT == MVT::f16 && !Subtarget->has16BitInsts()) { in LowerFLOGCommon()2802 assert(!Subtarget->has16BitInsts()); in lowerFEXP2()3327 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerUINT_TO_FP()3375 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerSINT_TO_FP()[all …]
150 if (Subtarget->has16BitInsts()) { in SITargetLowering()473 if (Subtarget->has16BitInsts()) { in SITargetLowering()550 if (Subtarget->has16BitInsts()) { in SITargetLowering()822 if (Subtarget->has16BitInsts()) { in SITargetLowering()997 if (Subtarget->has16BitInsts()) { in getRegisterTypeForCallingConv()1028 if (Size == 16 && Subtarget->has16BitInsts()) in getNumRegistersForCallingConv()1053 if (Size == 16 && Subtarget->has16BitInsts()) { in getVectorTypeBreakdownForCallingConv()1072 if (Size < 16 && Subtarget->has16BitInsts()) { in getVectorTypeBreakdownForCallingConv()10776 assert(!Subtarget->has16BitInsts()); in lowerFSQRTF16()12207 if (!Subtarget->has16BitInsts() || in performZeroExtendCombine()[all …]
1851 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
4123 return ST.has16BitInsts() && in isInlineConstant()4198 return ST.has16BitInsts() && in isInlineConstant()
1101 if (Size == 16 && !ST.has16BitInsts()) in getV_CMPOpcode()