150   if (Subtarget->has16BitInsts()) {  in SITargetLowering()
473   if (Subtarget->has16BitInsts()) {  in SITargetLowering()
550   if (Subtarget->has16BitInsts()) {  in SITargetLowering()
822   if (Subtarget->has16BitInsts()) {  in SITargetLowering()
915   if (Subtarget->has16BitInsts() && !Subtarget->hasMed3_16())  in SITargetLowering()
997       if (Subtarget->has16BitInsts()) {  in getRegisterTypeForCallingConv()
1006       return Subtarget->has16BitInsts() ? MVT::i16 : MVT::i32;  in getRegisterTypeForCallingConv()
1028     if (Size == 16 && Subtarget->has16BitInsts())  in getNumRegistersForCallingConv()
1053     if (Size == 16 && Subtarget->has16BitInsts()) {  in getVectorTypeBreakdownForCallingConv()
1072     if (Size < 16 && Subtarget->has16BitInsts()) {  in getVectorTypeBreakdownForCallingConv()
1877   if (Subtarget->has16BitInsts() && VT == MVT::i16) {  in isTypeDesirableForOp()
5341   return (Ty.getScalarSizeInBits() <= 16 && Subtarget->has16BitInsts())  in getPreferredShiftAmountTy()
5383     return Subtarget->has16BitInsts() && !denormalModeIsFlushAllF64F16(MF);  in isFMAFasterThanFMulAndFAdd()
10776   assert(!Subtarget->has16BitInsts());  in lowerFSQRTF16()
12207   if (!Subtarget->has16BitInsts() ||  in performZeroExtendCombine()
12945        (VT == MVT::f16 && Subtarget->has16BitInsts()) ||  in performMinMaxCombine()
13242   assert(Subtarget->has16BitInsts() && !Subtarget->hasMed3_16() &&  in performFPRoundCombine()
14083   if (VT != MVT::f16 || !Subtarget->has16BitInsts())  in performFDivCombine()
14253       (!Subtarget->has16BitInsts() || VT != MVT::f16))  in performSetCCCombine()
15209   if (Size == 16 && !Subtarget->has16BitInsts())  in getAsmOperandConstVal()