Home
last modified time | relevance | path

Searched refs:getSubReg (Results 1 – 25 of 161) sorted by relevance

1234567

/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp106 Register DstHi = TRI->getSubReg(Dst, PPC::sub_gp8_x0); in expandMI()
107 Register DstLo = TRI->getSubReg(Dst, PPC::sub_gp8_x1); in expandMI()
150 Register OldHi = TRI->getSubReg(Old, PPC::sub_gp8_x0); in expandAtomicRMW128()
151 Register OldLo = TRI->getSubReg(Old, PPC::sub_gp8_x1); in expandAtomicRMW128()
153 Register ScratchHi = TRI->getSubReg(Scratch, PPC::sub_gp8_x0); in expandAtomicRMW128()
154 Register ScratchLo = TRI->getSubReg(Scratch, PPC::sub_gp8_x1); in expandAtomicRMW128()
229 Register OldHi = TRI->getSubReg(Old, PPC::sub_gp8_x0); in expandAtomicCmpSwap128()
230 Register OldLo = TRI->getSubReg(Old, PPC::sub_gp8_x1); in expandAtomicCmpSwap128()
232 Register ScratchHi = TRI->getSubReg(Scratch, PPC::sub_gp8_x0); in expandAtomicCmpSwap128()
233 Register ScratchLo = TRI->getSubReg(Scratch, PPC::sub_gp8_x1); in expandAtomicCmpSwap128()
H A DPPCVSXFMAMutate.cpp221 unsigned AddSubReg = AddendMI->getOperand(1).getSubReg(); in processBlock()
222 unsigned KilledProdSubReg = MI.getOperand(KilledProdOp).getSubReg(); in processBlock()
223 unsigned OtherProdSubReg = MI.getOperand(OtherProdOp).getSubReg(); in processBlock()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DCalcSpillWeights.cpp54 Sub = MI->getOperand(0).getSubReg(); in copyHint()
56 HSub = MI->getOperand(1).getSubReg(); in copyHint()
58 Sub = MI->getOperand(1).getSubReg(); in copyHint()
60 HSub = MI->getOperand(0).getSubReg(); in copyHint()
70 MCRegister CopiedPReg = HSub ? TRI.getSubReg(HReg, HSub) : HReg.asMCReg(); in copyHint()
245 DestRegOp->getSubReg() == SrcRegOp->getSubReg(); in weightCalcHelper()
H A DPeepholeOptimizer.cpp557 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
997 if (MODef.getSubReg()) in getNextRewritableSource()
1040 if (MOExtractedReg.getSubReg()) in getNextRewritableSource()
1117 if ((Src.SubReg = MOInsertedReg.getSubReg())) in getNextRewritableSource()
1127 return MODef.getSubReg() == 0; in getNextRewritableSource()
1914 if (DefOp.getSubReg() != DefSubReg) in getNextSourceFromBitcast()
1957 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromRegSequence()
2001 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromInsertSubreg()
2092 if (Def->getOperand(2).getSubReg()) in getNextSourceFromSubregToReg()
2106 if (Def->getOperand(0).getSubReg() != DefSubReg) in getNextSourceFromPHI()
[all …]
H A DDetectDeadLanes.cpp77 unsigned SrcSubIdx = MO.getSubReg(); in isCrossCopy()
116 unsigned MOSubReg = MO.getSubReg(); in addUsedLanesOnOperand()
213 TRI->reverseComposeSubRegIndexLaneMask(Use.getSubReg(), DefinedLanes); in transferDefinedLanesStep()
262 assert(Def.getSubReg() == 0 && in transferDefinedLanes()
314 unsigned MOSubReg = MO.getSubReg(); in determineInitialDefinedLanes()
328 assert(Def.getSubReg() == 0 && in determineInitialDefinedLanes()
343 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes()
419 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput()
H A DExpandPostRAPseudos.cpp68 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); in LowerSubregToReg()
72 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
H A DRegAllocFast.cpp971 unsigned SubRegIdx = MO.getSubReg(); in allocVirtRegUndef()
973 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx); in allocVirtRegUndef()
1005 if (MO.getSubReg() && !MO.isUndef()) { in defineLiveThroughVirtReg()
1122 if (MI.isCopy() && MI.getOperand(1).getSubReg() == 0) { in useVirtReg()
1155 if (!MO.getSubReg()) { in setPhysReg()
1162 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : MCRegister()); in setPhysReg()
1322 (MO0.getSubReg() == 0 && !MO0.isUndef()); in findAndSortDefOperandIndexes()
1324 (MO1.getSubReg() == 0 && !MO1.isUndef()); in findAndSortDefOperandIndexes()
1383 if (isTiedToNotUndef(MO) || (MO.getSubReg() != 0 && !MO.isUndef())) in allocateInstruction()
1430 (MO.getSubReg() && !MO.isUndef())) { in allocateInstruction()
[all …]
H A DOptimizePHIs.cpp118 if (SrcMI && SrcMI->isCopy() && !SrcMI->getOperand(0).getSubReg() && in IsSingleValuePHICycle()
119 !SrcMI->getOperand(1).getSubReg() && in IsSingleValuePHICycle()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNRewritePartialRegUses.cpp136 unsigned getSubReg(unsigned Offset, unsigned Size) const;
165 unsigned GCNRewritePartialRegUses::getSubReg(unsigned Offset, in getSubReg() function in GCNRewritePartialRegUses
183 return getSubReg(Offset, TRI->getSubRegIdxSize(SubReg)); in shiftSubReg()
193 if (RCI.getSubReg() == SubRegIdx) { in getSuperRegClassMask()
414 return MO.getSubReg() == AMDGPU::NoSubRegister; // Whole reg used. [1] in rewriteReg()
426 const unsigned SubReg = MO.getSubReg(); in rewriteReg()
467 if (MO.isDebug() && MO.getSubReg() == 0) in rewriteReg()
469 unsigned SubReg = SubRegs[MO.getSubReg()].SubReg; in rewriteReg()
H A DGCNPreRAOptimizations.cpp120 Register SrcSubReg = I.getOperand(1).getSubReg(); in processReg()
122 if (SrcSubReg != Def.getOperand(0).getSubReg()) in processReg()
134 I.getOperand(1).setSubReg(DefSrcMO.getSubReg()); in processReg()
155 switch (I.getOperand(0).getSubReg()) { in processReg()
H A DR600ExpandSpecialInstrs.cpp211 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
212 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
217 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
218 Src0 = TRI.getSubReg(Src0, SubRegIndex0); in runOnMachineFunction()
226 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
H A DSIFoldOperands.cpp783 if (RSUse.getSubReg() != RegSeqDstSubReg) in foldOperand()
874 !UseMI->getOperand(1).getSubReg()) { in foldOperand()
1041 unsigned SubReg = OpToFold.getSubReg(); in foldOperand()
1072 if (UseOp.getSubReg() == AMDGPU::sub0) { in foldOperand()
1075 assert(UseOp.getSubReg() == AMDGPU::sub1); in foldOperand()
1512 Src0->getSubReg() != Src1->getSubReg() || in isClamp()
1681 Src0->getSubReg() == Src1->getSubReg() && in isOMod()
1760 while (UseMI->isCopy() && !Op->getSubReg()) { in tryFoldRegSequence()
1768 if (Op->getSubReg()) in tryFoldRegSequence()
1828 OutSubReg = CopySrc.getSubReg(); in isAGPRCopy()
[all …]
H A DSIFrameLowering.cpp184 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0); in buildGitPtr()
185 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1); in buildGitPtr()
426 FlatScrInitLo = TRI->getSubReg(FlatScrInit, AMDGPU::sub0); in emitEntryFunctionFlatScratchInit()
427 FlatScrInitHi = TRI->getSubReg(FlatScrInit, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
738 Register Rsrc03 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3); in emitEntryFunctionScratchRsrcRegSetup()
778 Register Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2); in emitEntryFunctionScratchRsrcRegSetup()
779 Register Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3); in emitEntryFunctionScratchRsrcRegSetup()
813 Register Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitEntryFunctionScratchRsrcRegSetup()
814 Register Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitEntryFunctionScratchRsrcRegSetup()
1679 SavedRegs.set(TRI->getSubReg(RetAddrReg, AMDGPU::sub0)); in determineCalleeSavesSGPR()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp140 inline MCRegister getSubReg(MCRegister Reg, unsigned Idx) const { in getSubReg() function in __anon315bf4520111::EliminateFrameIndex
141 return TRI.getSubReg(Reg, Idx); in getSubReg()
244 Register SrcHiReg = getSubReg(SrcReg, VE::sub_even); in processSTQ()
245 Register SrcLoReg = getSubReg(SrcReg, VE::sub_odd); in processSTQ()
265 Register DestHiReg = getSubReg(DestReg, VE::sub_even); in processLDQ()
266 Register DestLoReg = getSubReg(DestReg, VE::sub_odd); in processLDQ()
375 Register SrcLoReg = getSubReg(SrcReg, VE::sub_vm_odd); in processSTVM512()
376 Register SrcHiReg = getSubReg(SrcReg, VE::sub_vm_even); in processSTVM512()
421 Register DestLoReg = getSubReg(DestReg, VE::sub_vm_odd); in processLDVM512()
422 Register DestHiReg = getSubReg(DestReg, VE::sub_vm_even); in processLDVM512()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp33 MO.getSubReg() == SystemZ::subreg_ll32 || in getRC32()
34 MO.getSubReg() == SystemZ::subreg_l32) in getRC32()
37 MO.getSubReg() == SystemZ::subreg_lh32 || in getRC32()
38 MO.getSubReg() == SystemZ::subreg_h32) in getRC32()
113 if (MO->getSubReg()) in getRegAllocationHints()
114 PhysReg = getSubReg(PhysReg, MO->getSubReg()); in getRegAllocationHints()
115 if (VRRegMO->getSubReg()) in getRegAllocationHints()
116 PhysReg = getMatchingSuperReg(PhysReg, VRRegMO->getSubReg(), in getRegAllocationHints()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp144 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) in getSrcFromCopy()
148 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(), in getSrcFromCopy()
150 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), in getSrcFromCopy()
152 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp258 if (&MO == &Op || !MO.isReg() || MO.getSubReg()) in partitionRegisters()
319 if (!Op.getSubReg()) in profit()
323 if (MI->getOperand(1).getSubReg() != 0) in profit()
442 if (Op.getSubReg()) in isProfitable()
601 unsigned SR = Op.getSubReg(); in createHalfInstr()
672 assert(!UpdOp.getSubReg() && "Def operand with subreg"); in splitMemRef()
740 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg()); in splitCombine()
768 .addReg(Op1.getReg(), RS, Op1.getSubReg()) in splitExt()
1075 if (!Op.isReg() || !Op.isUse() || !Op.getSubReg()) in replaceSubregUses()
1082 switch (Op.getSubReg()) { in replaceSubregUses()
[all …]
H A DHexagonRDFOpt.cpp126 assert(DstOp.getSubReg() == 0 && "Unexpected subregister"); in INITIALIZE_PASS_DEPENDENCY()
128 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
130 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
142 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()), in INITIALIZE_PASS_DEPENDENCY()
143 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg())); in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonSplitConst32AndConst64.cpp87 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction()
88 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi); in runOnMachineFunction()
H A DHexagonAsmPrinter.cpp135 RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ? in PrintAsmOperand()
464 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
465 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
541 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
542 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
553 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
554 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
567 unsigned High = RI->getSubReg(MO.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
568 unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
H A DHexagonExpandCondsets.cpp181 Sub(Op.getSubReg()) {} in RegisterRef()
327 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg()); in updateKillFlags()
379 Register DR = Op.getReg(), DSR = Op.getSubReg(); in updateDeadsInRange()
614 MCRegister PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); in getCondTfrOpcode()
669 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
670 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg()); in genCondTfrFor()
674 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
696 Register DR = MD.getReg(), DSR = MD.getSubReg(); in split()
907 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); in predicateAt()
909 PredOp.getSubReg()); in predicateAt()
[all …]
H A DHexagonInstrInfo.cpp1173 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1188 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1195 HRI.getSubReg(DstReg, Hexagon::vsub_lo)) in expandPostRAPseudo()
1209 assert(SrcOp.getSubReg() == 0); in expandPostRAPseudo()
1211 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1227 assert(BaseOp.getSubReg() == 0); in expandPostRAPseudo()
1371 assert(Op1.getSubReg() == 0); in expandPostRAPseudo()
1404 assert(Op1.getSubReg() == 0); in expandPostRAPseudo()
2002 unsigned BaseSubA = BaseA.getSubReg(); in areMemAccessesTriviallyDisjoint()
2010 unsigned BaseSubB = BaseB.getSubReg(); in areMemAccessesTriviallyDisjoint()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.cpp196 Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64); in eliminateFrameIndex()
197 Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64); in eliminateFrameIndex()
208 Register DestEvenReg = getSubReg(DestReg, SP::sub_even64); in eliminateFrameIndex()
209 Register DestOddReg = getSubReg(DestReg, SP::sub_odd64); in eliminateFrameIndex()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp522 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
523 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
524 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
525 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
527 D0 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
528 D1 = TRI->getSubReg(Reg, ARM::dsub_5); in GetDSubRegs()
529 D2 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
530 D3 = TRI->getSubReg(Reg, ARM::dsub_7); in GetDSubRegs()
532 D0 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
533 D1 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/MC/
H A DMCRegisterInfo.cpp27 if (RC->contains(Super) && Reg == getSubReg(Super, SubIdx)) in getMatchingSuperReg()
32 MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const { in getSubReg() function in MCRegisterInfo

1234567